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Rename PTP clock timestamp signals to tod and rel

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2023-11-07 01:28:04 -08:00
parent 357dd26aae
commit c44f928bea
7 changed files with 288 additions and 264 deletions
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35
tests/ptp_clock_sim_time/test_ptp_clock_sim_time.py
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@@ -46,8 +46,8 @@ class TB:
cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
self.ptp_clock = PtpClockSimTime(
ts_96=dut.ts_96,
ts_64=dut.ts_64,
ts_tod=dut.ts_tod,
ts_rel=dut.ts_rel,
pps=dut.pps,
clock=dut.clk
)
@@ -63,30 +63,31 @@ async def run_test(dut):
await RisingEdge(dut.clk)
start_time = get_sim_time('sec')
start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
start_ts_tod = (dut.ts_tod.value.integer >> 48) + ((dut.ts_tod.value.integer & 0xffffffffffff)/2**16*1e-9)
start_ts_rel = dut.ts_rel.value.integer/2**16*1e-9
await ClockCycles(dut.clk, 10000)
stop_time = get_sim_time('sec')
stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
stop_ts_tod = (dut.ts_tod.value.integer >> 48) + ((dut.ts_tod.value.integer & 0xffffffffffff)/2**16*1e-9)
stop_ts_rel = dut.ts_rel.value.integer/2**16*1e-9
time_delta = stop_time-start_time
ts_96_delta = stop_ts_96-start_ts_96
ts_64_delta = stop_ts_64-start_ts_64
ts_tod_delta = stop_ts_tod-start_ts_tod
ts_rel_delta = stop_ts_rel-start_ts_rel
ts_96_diff = time_delta - ts_96_delta
ts_64_diff = time_delta - ts_64_delta
tb.log.info("sim time delta : %g s", time_delta)
tb.log.info("ToD ts delta : %g s", ts_tod_delta)
tb.log.info("rel ts delta : %g s", ts_rel_delta)
tb.log.info("sim time delta : %g s", time_delta)
tb.log.info("96 bit ts delta : %g s", ts_96_delta)
tb.log.info("64 bit ts delta : %g s", ts_64_delta)
tb.log.info("96 bit ts diff : %g s", ts_96_diff)
tb.log.info("64 bit ts diff : %g s", ts_64_diff)
ts_tod_diff = time_delta - ts_tod_delta
ts_rel_diff = time_delta - ts_rel_delta
assert abs(ts_96_diff) < 1e-12
assert abs(ts_64_diff) < 1e-12
tb.log.info("ToD ts diff : %g s", ts_tod_diff)
tb.log.info("rel ts diff : %g s", ts_rel_diff)
assert abs(ts_tod_diff) < 1e-12
assert abs(ts_rel_diff) < 1e-12
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

4
tests/ptp_clock_sim_time/test_ptp_clock_sim_time.v
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@@ -33,8 +33,8 @@ module test_ptp_clock_sim_time
(
input wire clk,
inout wire [95:0] ts_96,
inout wire [63:0] ts_64,
inout wire [95:0] ts_tod,
inout wire [63:0] ts_rel,
inout wire pps
);