Add PTP clock model
This commit is contained in:
Alex Forencich
326
tests/ptp_clock/test_ptp_clock.py
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326
tests/ptp_clock/test_ptp_clock.py
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#!/usr/bin/env python
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"""
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import logging
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import os
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.utils import get_sim_time
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from cocotbext.eth import PtpClock
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.fork(Clock(dut.clk, 6.4, units="ns").start())
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self.ptp_clock = PtpClock(
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ts_96=dut.ts_96,
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ts_64=dut.ts_64,
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ts_step=dut.ts_step,
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pps=dut.pps,
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clock=dut.clk,
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reset=dut.rst,
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period_ns=0x6,
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period_fns=0x6666,
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drift_ns=0x0,
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drift_fns=0x0002,
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drift_rate=5,
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)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst <= 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst <= 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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@cocotb.test()
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async def run_default_rate(dut):
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tb = TB(dut)
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await tb.reset()
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await RisingEdge(dut.clk)
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start_time = get_sim_time('sec')
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start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
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start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
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for k in range(10000):
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
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stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
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time_delta = stop_time-start_time
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ts_96_delta = stop_ts_96-start_ts_96
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ts_64_delta = stop_ts_64-start_ts_64
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ts_96_diff = time_delta - ts_96_delta
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ts_64_diff = time_delta - ts_64_delta
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tb.log.info("sim time delta : %g s", time_delta)
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tb.log.info("96 bit ts delta : %g s", ts_96_delta)
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tb.log.info("64 bit ts delta : %g s", ts_64_delta)
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tb.log.info("96 bit ts diff : %g s", ts_96_diff)
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tb.log.info("64 bit ts diff : %g s", ts_64_diff)
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assert abs(ts_96_diff) < 1e-12
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assert abs(ts_64_diff) < 1e-12
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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@cocotb.test()
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async def run_load_timestamps(dut):
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tb = TB(dut)
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await tb.reset()
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tb.ptp_clock.set_ts_96(12345678)
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tb.ptp_clock.set_ts_64(12345678)
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await RisingEdge(dut.clk)
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assert dut.ts_96.value.integer == 12345678+((tb.ptp_clock.period_ns << 16) + tb.ptp_clock.period_fns)
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assert dut.ts_64.value.integer == 12345678+((tb.ptp_clock.period_ns << 16) + tb.ptp_clock.period_fns)
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assert dut.ts_step.value.integer == 1
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start_time = get_sim_time('sec')
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start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
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start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
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for k in range(2000):
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
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stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
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time_delta = stop_time-start_time
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ts_96_delta = stop_ts_96-start_ts_96
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ts_64_delta = stop_ts_64-start_ts_64
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ts_96_diff = time_delta - ts_96_delta
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ts_64_diff = time_delta - ts_64_delta
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tb.log.info("sim time delta : %g s", time_delta)
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tb.log.info("96 bit ts delta : %g s", ts_96_delta)
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tb.log.info("64 bit ts delta : %g s", ts_64_delta)
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tb.log.info("96 bit ts diff : %g s", ts_96_diff)
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tb.log.info("64 bit ts diff : %g s", ts_64_diff)
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assert abs(ts_96_diff) < 1e-12
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assert abs(ts_64_diff) < 1e-12
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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@cocotb.test()
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async def run_seconds_increment(dut):
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tb = TB(dut)
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await tb.reset()
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tb.ptp_clock.set_ts_96(999990000*2**16)
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tb.ptp_clock.set_ts_64(999990000*2**16)
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await RisingEdge(dut.clk)
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start_time = get_sim_time('sec')
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start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
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start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
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saw_pps = False
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for k in range(3000):
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await RisingEdge(dut.clk)
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if dut.pps.value.integer:
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saw_pps = True
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assert dut.ts_96.value.integer >> 48 == 1
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assert dut.ts_96.value.integer & 0xffffffffffff < 10*2**16
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assert saw_pps
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stop_time = get_sim_time('sec')
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stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
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stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
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time_delta = stop_time-start_time
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ts_96_delta = stop_ts_96-start_ts_96
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ts_64_delta = stop_ts_64-start_ts_64
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ts_96_diff = time_delta - ts_96_delta
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ts_64_diff = time_delta - ts_64_delta
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tb.log.info("sim time delta : %g s", time_delta)
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tb.log.info("96 bit ts delta : %g s", ts_96_delta)
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tb.log.info("64 bit ts delta : %g s", ts_64_delta)
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tb.log.info("96 bit ts diff : %g s", ts_96_diff)
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tb.log.info("64 bit ts diff : %g s", ts_64_diff)
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assert abs(ts_96_diff) < 1e-12
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assert abs(ts_64_diff) < 1e-12
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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@cocotb.test()
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async def run_frequency_adjustment(dut):
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tb = TB(dut)
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await tb.reset()
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tb.ptp_clock.period_ns = 0x6
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tb.ptp_clock.period_fns = 0x6624
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await RisingEdge(dut.clk)
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start_time = get_sim_time('sec')
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start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
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start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
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for k in range(10000):
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
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stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
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time_delta = stop_time-start_time
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ts_96_delta = stop_ts_96-start_ts_96
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ts_64_delta = stop_ts_64-start_ts_64
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ts_96_diff = time_delta - ts_96_delta * 6.4/(6+(0x6624+2/5)/2**16)
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ts_64_diff = time_delta - ts_64_delta * 6.4/(6+(0x6624+2/5)/2**16)
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tb.log.info("sim time delta : %g s", time_delta)
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tb.log.info("96 bit ts delta : %g s", ts_96_delta)
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tb.log.info("64 bit ts delta : %g s", ts_64_delta)
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tb.log.info("96 bit ts diff : %g s", ts_96_diff)
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tb.log.info("64 bit ts diff : %g s", ts_64_diff)
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assert abs(ts_96_diff) < 1e-12
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assert abs(ts_64_diff) < 1e-12
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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@cocotb.test()
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async def run_drift_adjustment(dut):
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tb = TB(dut)
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await tb.reset()
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tb.ptp_clock.drift_ns = 0
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tb.ptp_clock.drift_fns = 20
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tb.ptp_clock.drift_rate = 5
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await RisingEdge(dut.clk)
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start_time = get_sim_time('sec')
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start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
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start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
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for k in range(10000):
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
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stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
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time_delta = stop_time-start_time
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ts_96_delta = stop_ts_96-start_ts_96
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ts_64_delta = stop_ts_64-start_ts_64
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ts_96_diff = time_delta - ts_96_delta * 6.4/(6+(0x6666+20/5)/2**16)
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ts_64_diff = time_delta - ts_64_delta * 6.4/(6+(0x6666+20/5)/2**16)
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tb.log.info("sim time delta : %g s", time_delta)
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tb.log.info("96 bit ts delta : %g s", ts_96_delta)
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tb.log.info("64 bit ts delta : %g s", ts_64_delta)
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tb.log.info("96 bit ts diff : %g s", ts_96_diff)
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tb.log.info("64 bit ts diff : %g s", ts_64_diff)
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assert abs(ts_96_diff) < 1e-12
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assert abs(ts_64_diff) < 1e-12
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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# cocotb-test
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tests_dir = os.path.dirname(__file__)
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
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def test_ptp_clock(request):
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dut = "test_ptp_clock"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(tests_dir, f"{dut}.v"),
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]
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parameters = {}
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir,
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"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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