Add PTP clock model

cocotbext/eth/__init__.py

@@ -27,3 +27,5 @@ from .version import __version__
 from .gmii import GmiiFrame, GmiiSource, GmiiSink
 from .rgmii import RgmiiSource, RgmiiSink
 from .xgmii import XgmiiFrame, XgmiiSource, XgmiiSink
+
+from .ptp import PtpClock

cocotbext/eth/ptp.py

@@ -0,0 +1,220 @@
+"""
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+import logging
+import math
+
+import cocotb
+from cocotb.triggers import RisingEdge, ReadOnly
+
+from .version import __version__
+
+
+class PtpClock(object):
+
+    def __init__(
+            self,
+            ts_96=None,
+            ts_64=None,
+            ts_step=None,
+            pps=None,
+            clock=None,
+            reset=None,
+            period_ns=0x6,
+            period_fns=0x6666,
+            drift_ns=0x0,
+            drift_fns=0x0002,
+            drift_rate=5,
+            *args, **kwargs):
+
+        self.log = logging.getLogger(f"cocotb.eth.{type(self).__name__}")
+        self.ts_96 = ts_96
+        self.ts_64 = ts_64
+        self.ts_step = ts_step
+        self.pps = pps
+        self.clock = clock
+        self.reset = reset
+
+        self.period_ns = period_ns
+        self.period_fns = period_fns
+        self.drift_ns = drift_ns
+        self.drift_fns = drift_fns
+        self.drift_rate = drift_rate
+
+        self.log.info("PTP clock")
+        self.log.info("cocotbext-eth version %s", __version__)
+        self.log.info("Copyright (c) 2020 Alex Forencich")
+        self.log.info("https://github.com/alexforencich/cocotbext-eth")
+
+        super().__init__(*args, **kwargs)
+
+        self.ts_96_s = 0
+        self.ts_96_ns = 0
+        self.ts_96_fns = 0
+
+        self.ts_64_ns = 0
+        self.ts_64_fns = 0
+
+        self.ts_updated = False
+
+        self.drift_cnt = 0
+
+        if self.ts_96 is not None:
+            self.ts_96.setimmediatevalue(0)
+        if self.ts_64 is not None:
+            self.ts_64.setimmediatevalue(0)
+        if self.ts_step is not None:
+            self.ts_step.setimmediatevalue(0)
+        if self.pps is not None:
+            self.pps.setimmediatevalue(0)
+
+        cocotb.fork(self._run())
+
+    def set_ts_96(self, ts_s, ts_ns=None, ts_fns=None):
+        ts_s = int(ts_s)
+        if ts_fns is not None:
+            # got separate fields
+            self.ts_96_s = ts_s
+            self.ts_96_ns = int(ts_ns)
+            self.ts_96_fns = int(ts_fns)
+        else:
+            # got timestamp as integer
+            self.ts_96_s = ts_s >> 48
+            self.ts_96_ns = (ts_s >> 16) & 0x3fffffff
+            self.ts_96_fns = ts_s & 0xffff
+        self.ts_updated = True
+
+    def set_ts_96_ns(self, t):
+        self.set_ts_96_s(t*1e-9)
+
+    def set_ts_96_s(self, t):
+        ts_ns, ts_s = math.modf(t)
+        ts_ns *= 1e9
+        ts_fns, ts_ns = math.modf(ts_ns)
+        ts_fns *= 2**16
+        self.set_ts_96(ts_s, ts_ns, ts_fns)
+
+    def get_ts_96(self):
+        return (self.ts_96_s << 48) | (self.ts_96_ns << 16) | self.ts_96_fns
+
+    def get_ts_96_ns(self):
+        return self.ts_96_s*1e9+self.ts_96_ns+self.ts_96_fns/2**16
+
+    def get_ts_96_s(self):
+        return self.get_ts_96_ns()*1e-9
+
+    def set_ts_64(self, ts_ns, ts_fns=None):
+        ts_ns = int(ts_ns)
+        if ts_fns is not None:
+            # got separate fields
+            self.ts_64_ns = ts_ns
+            self.ts_64_fns = int(ts_fns)
+        else:
+            # got timestamp as integer
+            self.ts_64_ns = ts_ns >> 16
+            self.ts_64_fns = ts_ns & 0xffff
+        self.ts_updated = True
+
+    def set_ts_64_ns(self, t):
+        self.set_ts_64(t*2**16)
+
+    def set_ts_64_s(self, t):
+        self.set_ts_64_ns(t*1e9)
+
+    def get_ts_64(self):
+        return (self.ts_64_ns << 16) | self.ts_64_fns
+
+    def get_ts_64_ns(self):
+        return self.get_ts_64()/2**16
+
+    def get_ts_64_s(self):
+        return self.get_ts_64()*1e-9
+
+    async def _run(self):
+        while True:
+            await ReadOnly()
+
+            if self.reset is not None and self.reset.value:
+                await RisingEdge(self.clock)
+                self.ts_96_s = 0
+                self.ts_96_ns = 0
+                self.ts_96_fns = 0
+                self.ts_64_ns = 0
+                self.ts_64_fns = 0
+                self.drift_cnt = 0
+                if self.ts_96 is not None:
+                    self.ts_96 <= 0
+                if self.ts_64 is not None:
+                    self.ts_64 <= 0
+                if self.ts_step is not None:
+                    self.ts_step <= 0
+                if self.pps is not None:
+                    self.pps <= 0
+                continue
+
+            await RisingEdge(self.clock)
+
+            if self.ts_step is not None:
+                self.ts_step <= self.ts_updated
+                self.ts_updated = False
+
+            if self.pps is not None:
+                self.pps <= 0
+
+            # increment 96 bit timestamp
+            if self.ts_96 is not None or self.pps is not None:
+                t = ((self.ts_96_ns << 16) + self.ts_96_fns) + ((self.period_ns << 16) + self.period_fns)
+
+                if self.drift_rate and self.drift_cnt == 0:
+                    t += (self.drift_ns << 16) + self.drift_fns
+
+                if t > (1000000000 << 16):
+                    self.ts_96_s += 1
+                    t -= (1000000000 << 16)
+                    if self.pps is not None:
+                        self.pps <= 1
+
+                self.ts_96_fns = t & 0xffff
+                self.ts_96_ns = t >> 16
+
+                if self.ts_96 is not None:
+                    self.ts_96 <= (self.ts_96_s << 48) | (self.ts_96_ns << 16) | (self.ts_96_fns)
+
+            # increment 64 bit timestamp
+            if self.ts_64 is not None:
+                t = ((self.ts_64_ns << 16) + self.ts_64_fns) + ((self.period_ns << 16) + self.period_fns)
+
+                if self.drift_rate and self.drift_cnt == 0:
+                    t += ((self.drift_ns << 16) + self.drift_fns)
+
+                self.ts_64_fns = t & 0xffff
+                self.ts_64_ns = t >> 16
+
+                self.ts_64 <= (self.ts_64_ns << 16) | self.ts_64_fns
+
+            if self.drift_rate:
+                if self.drift_cnt > 0:
+                    self.drift_cnt -= 1
+                else:
+                    self.drift_cnt = self.drift_rate-1

tests/ptp_clock/Makefile

@@ -0,0 +1,65 @@
+# Copyright (c) 2020 Alex Forencich
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= icarus
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = test_ptp_clock
+TOPLEVEL = $(DUT)
+MODULE   = $(DUT)
+VERILOG_SOURCES += $(DUT).v
+
+SIM_BUILD ?= sim_build_$(MODULE)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	ifeq ($(WAVES), 1)
+		VERILOG_SOURCES += iverilog_dump.v
+		COMPILE_ARGS += -s iverilog_dump
+	endif
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+	endif
+endif
+
+iverilog_dump.v:
+	echo 'module iverilog_dump();' > $@
+	echo 'initial begin' >> $@
+	echo '    $$dumpfile("$(TOPLEVEL).fst");' >> $@
+	echo '    $$dumpvars(0, $(TOPLEVEL));' >> $@
+	echo 'end' >> $@
+	echo 'endmodule' >> $@
+
+clean::
+	@rm -rf sim_build_*
+	@rm -rf iverilog_dump.v
+	@rm -rf dump.fst $(TOPLEVEL).fst
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+

tests/ptp_clock/test_ptp_clock.py

@@ -0,0 +1,326 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_sim_time
+
+from cocotbext.eth import PtpClock
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.fork(Clock(dut.clk, 6.4, units="ns").start())
+
+        self.ptp_clock = PtpClock(
+            ts_96=dut.ts_96,
+            ts_64=dut.ts_64,
+            ts_step=dut.ts_step,
+            pps=dut.pps,
+            clock=dut.clk,
+            reset=dut.rst,
+            period_ns=0x6,
+            period_fns=0x6666,
+            drift_ns=0x0,
+            drift_fns=0x0002,
+            drift_rate=5,
+        )
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst <= 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst <= 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+@cocotb.test()
+async def run_default_rate(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    await RisingEdge(dut.clk)
+    start_time = get_sim_time('sec')
+    start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
+    start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
+
+    for k in range(10000):
+        await RisingEdge(dut.clk)
+
+    stop_time = get_sim_time('sec')
+    stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
+    stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
+
+    time_delta = stop_time-start_time
+    ts_96_delta = stop_ts_96-start_ts_96
+    ts_64_delta = stop_ts_64-start_ts_64
+
+    ts_96_diff = time_delta - ts_96_delta
+    ts_64_diff = time_delta - ts_64_delta
+
+    tb.log.info("sim time delta  : %g s", time_delta)
+    tb.log.info("96 bit ts delta : %g s", ts_96_delta)
+    tb.log.info("64 bit ts delta : %g s", ts_64_delta)
+    tb.log.info("96 bit ts diff  : %g s", ts_96_diff)
+    tb.log.info("64 bit ts diff  : %g s", ts_64_diff)
+
+    assert abs(ts_96_diff) < 1e-12
+    assert abs(ts_64_diff) < 1e-12
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+@cocotb.test()
+async def run_load_timestamps(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.ptp_clock.set_ts_96(12345678)
+    tb.ptp_clock.set_ts_64(12345678)
+
+    await RisingEdge(dut.clk)
+
+    assert dut.ts_96.value.integer == 12345678+((tb.ptp_clock.period_ns << 16) + tb.ptp_clock.period_fns)
+    assert dut.ts_64.value.integer == 12345678+((tb.ptp_clock.period_ns << 16) + tb.ptp_clock.period_fns)
+    assert dut.ts_step.value.integer == 1
+
+    start_time = get_sim_time('sec')
+    start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
+    start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
+
+    for k in range(2000):
+        await RisingEdge(dut.clk)
+
+    stop_time = get_sim_time('sec')
+    stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
+    stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
+
+    time_delta = stop_time-start_time
+    ts_96_delta = stop_ts_96-start_ts_96
+    ts_64_delta = stop_ts_64-start_ts_64
+
+    ts_96_diff = time_delta - ts_96_delta
+    ts_64_diff = time_delta - ts_64_delta
+
+    tb.log.info("sim time delta  : %g s", time_delta)
+    tb.log.info("96 bit ts delta : %g s", ts_96_delta)
+    tb.log.info("64 bit ts delta : %g s", ts_64_delta)
+    tb.log.info("96 bit ts diff  : %g s", ts_96_diff)
+    tb.log.info("64 bit ts diff  : %g s", ts_64_diff)
+
+    assert abs(ts_96_diff) < 1e-12
+    assert abs(ts_64_diff) < 1e-12
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+@cocotb.test()
+async def run_seconds_increment(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.ptp_clock.set_ts_96(999990000*2**16)
+    tb.ptp_clock.set_ts_64(999990000*2**16)
+
+    await RisingEdge(dut.clk)
+    start_time = get_sim_time('sec')
+    start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
+    start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
+
+    saw_pps = False
+
+    for k in range(3000):
+        await RisingEdge(dut.clk)
+
+        if dut.pps.value.integer:
+            saw_pps = True
+            assert dut.ts_96.value.integer >> 48 == 1
+            assert dut.ts_96.value.integer & 0xffffffffffff < 10*2**16
+
+    assert saw_pps
+
+    stop_time = get_sim_time('sec')
+    stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
+    stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
+
+    time_delta = stop_time-start_time
+    ts_96_delta = stop_ts_96-start_ts_96
+    ts_64_delta = stop_ts_64-start_ts_64
+
+    ts_96_diff = time_delta - ts_96_delta
+    ts_64_diff = time_delta - ts_64_delta
+
+    tb.log.info("sim time delta  : %g s", time_delta)
+    tb.log.info("96 bit ts delta : %g s", ts_96_delta)
+    tb.log.info("64 bit ts delta : %g s", ts_64_delta)
+    tb.log.info("96 bit ts diff  : %g s", ts_96_diff)
+    tb.log.info("64 bit ts diff  : %g s", ts_64_diff)
+
+    assert abs(ts_96_diff) < 1e-12
+    assert abs(ts_64_diff) < 1e-12
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+@cocotb.test()
+async def run_frequency_adjustment(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.ptp_clock.period_ns = 0x6
+    tb.ptp_clock.period_fns = 0x6624
+
+    await RisingEdge(dut.clk)
+    start_time = get_sim_time('sec')
+    start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
+    start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
+
+    for k in range(10000):
+        await RisingEdge(dut.clk)
+
+    stop_time = get_sim_time('sec')
+    stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
+    stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
+
+    time_delta = stop_time-start_time
+    ts_96_delta = stop_ts_96-start_ts_96
+    ts_64_delta = stop_ts_64-start_ts_64
+
+    ts_96_diff = time_delta - ts_96_delta * 6.4/(6+(0x6624+2/5)/2**16)
+    ts_64_diff = time_delta - ts_64_delta * 6.4/(6+(0x6624+2/5)/2**16)
+
+    tb.log.info("sim time delta  : %g s", time_delta)
+    tb.log.info("96 bit ts delta : %g s", ts_96_delta)
+    tb.log.info("64 bit ts delta : %g s", ts_64_delta)
+    tb.log.info("96 bit ts diff  : %g s", ts_96_diff)
+    tb.log.info("64 bit ts diff  : %g s", ts_64_diff)
+
+    assert abs(ts_96_diff) < 1e-12
+    assert abs(ts_64_diff) < 1e-12
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+@cocotb.test()
+async def run_drift_adjustment(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.ptp_clock.drift_ns = 0
+    tb.ptp_clock.drift_fns = 20
+    tb.ptp_clock.drift_rate = 5
+
+    await RisingEdge(dut.clk)
+    start_time = get_sim_time('sec')
+    start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
+    start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
+
+    for k in range(10000):
+        await RisingEdge(dut.clk)
+
+    stop_time = get_sim_time('sec')
+    stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
+    stop_ts_64 = dut.ts_64.value.integer/2**16*1e-9
+
+    time_delta = stop_time-start_time
+    ts_96_delta = stop_ts_96-start_ts_96
+    ts_64_delta = stop_ts_64-start_ts_64
+
+    ts_96_diff = time_delta - ts_96_delta * 6.4/(6+(0x6666+20/5)/2**16)
+    ts_64_diff = time_delta - ts_64_delta * 6.4/(6+(0x6666+20/5)/2**16)
+
+    tb.log.info("sim time delta  : %g s", time_delta)
+    tb.log.info("96 bit ts delta : %g s", ts_96_delta)
+    tb.log.info("64 bit ts delta : %g s", ts_64_delta)
+    tb.log.info("96 bit ts diff  : %g s", ts_96_diff)
+    tb.log.info("64 bit ts diff  : %g s", ts_64_diff)
+
+    assert abs(ts_96_diff) < 1e-12
+    assert abs(ts_64_diff) < 1e-12
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+# cocotb-test
+
+tests_dir = os.path.dirname(__file__)
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+
+
+def test_ptp_clock(request):
+    dut = "test_ptp_clock"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{dut}.v"),
+    ]
+
+    parameters = {}
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir,
+        "sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tests/ptp_clock/test_ptp_clock.v

@@ -0,0 +1,43 @@
+/*
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * PTP clock test
+ */
+module test_ptp_clock
+(
+    input  wire        clk,
+    input  wire        rst,
+
+    inout  wire [95:0] ts_96,
+    inout  wire [63:0] ts_64,
+    inout  wire        ts_step,
+    inout  wire        pps
+);
+
+endmodule