66 lines
2.5 KiB
Verilog
66 lines
2.5 KiB
Verilog
/*
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Copyright (c) 2021-2025 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Ethernet MAC model test
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*/
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module test_eth_mac #
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(
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parameter PTP_TS_WIDTH = 96,
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parameter PTP_TAG_WIDTH = 16,
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parameter AXIS_DATA_WIDTH = 64,
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parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
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parameter AXIS_TX_USER_WIDTH = PTP_TAG_WIDTH+1,
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parameter AXIS_RX_USER_WIDTH = PTP_TS_WIDTH+1
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)
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(
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inout wire tx_clk,
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inout wire tx_rst,
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inout wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
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inout wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
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inout wire tx_axis_tlast,
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inout wire [AXIS_TX_USER_WIDTH-1:0] tx_axis_tuser,
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inout wire tx_axis_tvalid,
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inout wire tx_axis_tready,
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inout wire [PTP_TS_WIDTH-1:0] tx_ptp_time,
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inout wire [PTP_TS_WIDTH-1:0] tx_ptp_ts,
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inout wire [PTP_TAG_WIDTH-1:0] tx_ptp_ts_tag,
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inout wire tx_ptp_ts_valid,
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inout wire rx_clk,
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inout wire rx_rst,
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inout wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
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inout wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
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inout wire rx_axis_tlast,
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inout wire [AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser,
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inout wire rx_axis_tvalid,
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inout wire [PTP_TS_WIDTH-1:0] rx_ptp_time
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);
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endmodule
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