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Arlet 65C02 WIP: Implement TSB/TXB

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Change-Id: I3a452d03a4f8872f3b0232e174ec9dbcb5ec4f0f
This commit is contained in:
David Banks
2016-08-01 12:00:29 +01:00
parent c5f486730e
commit 05e5f633f7
1 changed files with 43 additions and 5 deletions
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44
cpu_65c02.v
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@@ -55,6 +55,7 @@ reg D = 0; // decimal flag
reg V = 0; // overflow flag reg V = 0; // overflow flag
reg N = 0; // negative flag reg N = 0; // negative flag
wire AZ; // ALU Zero flag wire AZ; // ALU Zero flag
reg AZ2; // ALU Second Zero flag, set using TSB/TRB semantics
wire AV; // ALU overflow flag wire AV; // ALU overflow flag
wire AN; // ALU negative flag wire AN; // ALU negative flag
wire HC; // ALU half carry wire HC; // ALU half carry
@@ -136,6 +137,8 @@ reg adj_bcd; // results should be BCD adjusted
* get loaded at the DECODE state, and used later * get loaded at the DECODE state, and used later
*/ */
reg store_zero; // doing STZ instruction reg store_zero; // doing STZ instruction
reg trb_ins; // doing TRB instruction
reg txb_ins; // doing TSB/TRB instruction
reg bit_ins; // doing BIT instruction reg bit_ins; // doing BIT instruction
reg bit_ins_nv; // doing BIT instruction that will update the n and v flags (i.e. not BIT imm) reg bit_ins_nv; // doing BIT instruction that will update the n and v flags (i.e. not BIT imm)
reg plp; // doing PLP instruction reg plp; // doing PLP instruction
@@ -683,7 +686,6 @@ always @*
RTI1, RTI1,
RTI2, RTI2,
INDX1, INDX1,
READ,
REG, REG,
JSR0, JSR0,
JSR1, JSR1,
@@ -696,6 +698,8 @@ always @*
PULL0, PULL0,
RTS0: BI = 8'h00; RTS0: BI = 8'h00;
READ: BI = txb_ins ? (trb_ins ? ~regfile : regfile) : 8'h00;
BRA0: BI = PCL; BRA0: BI = PCL;
DECODE, DECODE,
@@ -761,13 +765,19 @@ always @(posedge clk )
end end
end end
/*
* Special Z flag got TRB/TSB
*/
always @(posedge clk)
AZ2 <= ~|(AI & regfile);
/* /*
* Update Z, N flags when writing A, X, Y, Memory, or when doing compare * Update Z, N flags when writing A, X, Y, Memory, or when doing compare
*/ */
always @(posedge clk) always @(posedge clk)
if( state == WRITE) if( state == WRITE)
Z <= AZ; Z <= txb_ins ? AZ2 : AZ;
else if( state == RTI2 ) else if( state == RTI2 )
Z <= DIMUX[1]; Z <= DIMUX[1];
else if( state == DECODE ) begin else if( state == DECODE ) begin
@@ -778,7 +788,7 @@ always @(posedge clk)
end end
always @(posedge clk) always @(posedge clk)
if( state == WRITE ) if( state == WRITE && ~txb_ins)
N <= AN; N <= AN;
else if( state == RTI2 ) else if( state == RTI2 )
N <= DIMUX[7]; N <= DIMUX[7];
@@ -876,10 +886,12 @@ always @(posedge clk or posedge reset)
else if( RDY ) case( state ) else if( RDY ) case( state )
DECODE : DECODE :
casex ( IR ) casex ( IR )
// TODO Review for simplifications as in verilog the first matching case has priority
8'b0000_0000: state <= BRK0; 8'b0000_0000: state <= BRK0;
8'b0010_0000: state <= JSR0; 8'b0010_0000: state <= JSR0;
8'b0010_1100: state <= ABS0; // BIT abs 8'b0010_1100: state <= ABS0; // BIT abs
8'b1001_1100: state <= ABS0; // STZ abs 8'b1001_1100: state <= ABS0; // STZ abs
8'b000x_1100: state <= ABS0; // TSB/TRB
8'b0100_0000: state <= RTI0; // 8'b0100_0000: state <= RTI0; //
8'b0100_1100: state <= JMP0; 8'b0100_1100: state <= JMP0;
8'b0110_0000: state <= RTS0; 8'b0110_0000: state <= RTS0;
@@ -893,6 +905,7 @@ always @(posedge clk or posedge reset)
8'b1xxx_1000: state <= REG; // DEY, TYA, ... 8'b1xxx_1000: state <= REG; // DEY, TYA, ...
8'bxxx0_0001: state <= INDX0; 8'bxxx0_0001: state <= INDX0;
8'bxxx1_0010: state <= IND0; // (ZP) odd 2 column 8'bxxx1_0010: state <= IND0; // (ZP) odd 2 column
8'b000x_0100: state <= ZP0; // TSB/TRB
8'bxxx0_01xx: state <= ZP0; 8'bxxx0_01xx: state <= ZP0;
8'bxxx0_1001: state <= FETCH; // IMM 8'bxxx0_1001: state <= FETCH; // IMM
8'bxxx0_1101: state <= ABS0; // even D column 8'bxxx0_1101: state <= ABS0; // even D column
@@ -1089,6 +1102,7 @@ always @(posedge clk )
if( state == DECODE && RDY ) if( state == DECODE && RDY )
casex( IR ) casex( IR )
8'b0xxx_x110, // ASL, ROL, LSR, ROR 8'b0xxx_x110, // ASL, ROL, LSR, ROR
8'b000x_x100, // TSB/TRB
8'b11xx_x110: // DEC/INC 8'b11xx_x110: // DEC/INC
write_back <= 1; write_back <= 1;
@@ -1180,6 +1194,12 @@ always @(posedge clk )
always @(posedge clk ) always @(posedge clk )
if( state == DECODE && RDY ) if( state == DECODE && RDY )
casex( IR ) casex( IR )
8'b0000_x100: // TSB
op <= OP_OR;
8'b0001_x100: // TRB
op <= OP_AND;
8'b00xx_x110, // ROL, ASL 8'b00xx_x110, // ROL, ASL
8'b00x0_1010: // ROL, ASL 8'b00x0_1010: // ROL, ASL
op <= OP_ROL; op <= OP_ROL;
@@ -1223,6 +1243,24 @@ always @(posedge clk )
{bit_ins, bit_ins_nv} <= 2'b00; {bit_ins, bit_ins_nv} <= 2'b00;
endcase endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b000x_x100: // TRB/TSB
txb_ins <= 1;
default: txb_ins <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0001_x100: // TRB
trb_ins <= 1;
default: trb_ins <= 0;
endcase
always @(posedge clk ) always @(posedge clk )
if( state == DECODE && RDY ) if( state == DECODE && RDY )
casex( IR ) casex( IR )