third-party/verilog-6502
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Fix syntax error

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This commit is contained in:
Arlet Ottens
2012-10-06 16:20:49 +02:00
parent 3a0dfb7336
commit 071e7fc9be
1 changed files with 2 additions and 2 deletions
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4
cpu.v
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@@ -980,12 +980,12 @@ always @(posedge clk)
8'b0xx01010, // ASLA, ROLA, LSRA, RORA 8'b0xx01010, // ASLA, ROLA, LSRA, RORA
8'b0xxxxx01, // ORA, AND, EOR, ADC 8'b0xxxxx01, // ORA, AND, EOR, ADC
8'b100x10x0, // DEY, TYA, TXA, TXS 8'b100x10x0, // DEY, TYA, TXA, TXS
8'b1010xxx0: // LDA/LDX/LDY 8'b1010xxx0, // LDA/LDX/LDY
8'b10111010, // TSX 8'b10111010, // TSX
8'b1011x1x0, // LDX/LDY 8'b1011x1x0, // LDX/LDY
8'b11001010, // DEX 8'b11001010, // DEX
8'b1x1xxx01, // LDA, SBC 8'b1x1xxx01, // LDA, SBC
8'bxxx01000, // DEY, TAY, INY, INX 8'bxxx01000: // DEY, TAY, INY, INX
load_reg <= 1; load_reg <= 1;
default: load_reg <= 0; default: load_reg <= 0;