third-party/verilog-6502
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Make SEI/CLI take effect one cycle earlier.

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Arlet
2011-09-27 07:17:15 +02:00
parent 9b58705596
commit 3678fc4f4e
1 changed files with 2 additions and 2 deletions
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4
cpu.v
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@@ -795,11 +795,11 @@ always @(posedge clk)
I <= 1; I <= 1;
else if( state == RTI2 ) else if( state == RTI2 )
I <= DIMUX[2]; I <= DIMUX[2];
else if( state == DECODE ) begin else if( state == REG ) begin
if( sei ) I <= 1; if( sei ) I <= 1;
if( cli ) I <= 0; if( cli ) I <= 0;
else if( state == DECODE )
if( plp ) I <= ADD[2]; if( plp ) I <= ADD[2];
end
/* /*
* Update D flag * Update D flag