From 473b5bdcab16641833ab883bb79a0c55e6f94926 Mon Sep 17 00:00:00 2001 From: David Banks Date: Mon, 1 Aug 2016 11:58:14 +0100 Subject: [PATCH] Arlet 65C02 WIP: Cosmetic Change-Id: I9c9c1d612f254fd7c36a6d3425c6824fcbfc7c3c --- cpu_65c02.v | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/cpu_65c02.v b/cpu_65c02.v index e1ce704..f882080 100644 --- a/cpu_65c02.v +++ b/cpu_65c02.v @@ -989,18 +989,18 @@ always @(posedge clk) always @(posedge clk) if( state == DECODE && RDY ) casex( IR ) - 8'b0xx10010, // ORA, AND, EOR, ADC (zp) - 8'b1x110010, // LDA, SBC (zp) - 8'b0xxx1010, // ASLA, INCA, ROLA, DECA, LSRA, PHY, RORA, PLY - 8'b0xxxxx01, // ORA, AND, EOR, ADC - 8'b100x10x0, // DEY, TYA, TXA, TXS - 8'b1010xxx0, // LDA/LDX/LDY - 8'b10111010, // TSX - 8'b1011x1x0, // LDX/LDY - 8'b11001010, // DEX - 8'b11x11010, // PHX, PLX - 8'b1x1xxx01, // LDA, SBC - 8'bxxx01000: // PHP, PLP, PHA, PLA, DEY, TAY, INY, INX + 8'b0xx1_0010, // ORA, AND, EOR, ADC (zp) + 8'b1x11_0010, // LDA, SBC (zp) + 8'b0xxx_1010, // ASLA, INCA, ROLA, DECA, LSRA, PHY, RORA, PLY + 8'b0xxx_xx01, // ORA, AND, EOR, ADC + 8'b100x_10x0, // DEY, TYA, TXA, TXS + 8'b1010_xxx0, // LDA/LDX/LDY + 8'b1011_1010, // TSX + 8'b1011_x1x0, // LDX/LDY + 8'b1100_1010, // DEX + 8'b11x1_1010, // PHX, PLX + 8'b1x1x_xx01, // LDA, SBC + 8'bxxx0_1000: // PHP, PLP, PHA, PLA, DEY, TAY, INY, INX load_reg <= 1; default: load_reg <= 0;