From a11631082b20e8a0746cd5cc4ae8bbe68bff79c4 Mon Sep 17 00:00:00 2001
From: Arlet Ottens <arlet@ladybug.xs4all.nl>
Date: Fri, 19 Aug 2016 20:19:40 +0200
Subject: [PATCH 1/2] Added fix for 1-cycle RDY bug

---
 cpu.v | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/cpu.v b/cpu.v
index a08804f..ed8da62 100644
--- a/cpu.v
+++ b/cpu.v
@@ -836,15 +836,6 @@ always @(posedge clk )
  * time to read the IR again before the next decode.
  */
 
-reg RDY1 = 1;
-
-always @(posedge clk )
-    RDY1 <= RDY;
-
-always @(posedge clk )
-    if( ~RDY && RDY1 )
-        DIHOLD <= DI;
-
 always @(posedge clk )
     if( reset )
         IRHOLD_valid <= 0;
@@ -859,7 +850,11 @@ always @(posedge clk )
 assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 :
                      IRHOLD_valid ? IRHOLD : DIMUX;
 
-assign DIMUX = ~RDY1 ? DIHOLD : DI;
+always @(posedge clk )
+    if( RDY )
+        DIHOLD <= DI;
+
+assign DIMUX = ~RDY ? DIHOLD : DI;
 
 /*
  * Microcode state machine

From e6f361d7644f6b994165c3839910022bc3d0fa9a Mon Sep 17 00:00:00 2001
From: Arlet Ottens <arlet@ladybug.xs4all.nl>
Date: Wed, 21 Oct 2020 12:12:56 +0200
Subject: [PATCH 2/2] Updated README

---
 README => README.md | 2 ++
 1 file changed, 2 insertions(+)
 rename README => README.md (81%)

diff --git a/README b/README.md
similarity index 81%
rename from README
rename to README.md
index 3de3c7c..67256ce 100644
--- a/README
+++ b/README.md
@@ -5,4 +5,6 @@ data (DI) is expected on the cycle *after* valid address. This allows
 direct connection to (Xilinx) block RAMs. When using asynchronous memory,
 I suggest registering the address/control lines for glitchless output signals.
 
+[Also check out my new 65C02 project](https://github.com/Arlet/verilog-65c02)
+
 Have fun.