third-party/verilog-6502
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fixed typo

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Arlet
2011-10-02 12:23:40 +02:00
parent 3678fc4f4e
commit 6796444f2c
1 changed files with 1 additions and 1 deletions
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cpu.v
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@@ -798,7 +798,7 @@ always @(posedge clk)
else if( state == REG ) begin else if( state == REG ) begin
if( sei ) I <= 1; if( sei ) I <= 1;
if( cli ) I <= 0; if( cli ) I <= 0;
else if( state == DECODE ) end else if( state == DECODE )
if( plp ) I <= ADD[2]; if( plp ) I <= ADD[2];
/* /*