From 791ed43bae4ab8881f8e73f61f5b02dd17898372 Mon Sep 17 00:00:00 2001
From: David Banks <dave@hoglet.com>
Date: Mon, 1 Aug 2016 12:36:46 +0100
Subject: [PATCH] Updated README and 65C02 Copyright

Change-Id: I88efe06d7959744165c35b54edf6e3633ff05406
---
 README      | 69 +++++++++++++++++++++++++++++++++++++++++++++++++----
 cpu_65c02.v | 14 +++++++++--
 2 files changed, 76 insertions(+), 7 deletions(-)

diff --git a/README b/README
index 3de3c7c..dc2056b 100644
--- a/README
+++ b/README
@@ -1,8 +1,67 @@
-A Verilog HDL version of the old MOS 6502 CPU.
+========================================================
+A Verilog HDL version of the old MOS 6502 and 65C02 CPUs
+========================================================
 
-Note: the 6502 core assumes a synchronous memory. This means that valid
-data (DI) is expected on the cycle *after* valid address. This allows
-direct connection to (Xilinx) block RAMs. When using asynchronous memory,
-I suggest registering the address/control lines for glitchless output signals.
+Original 6502 core by Arlet Ottens
+
+65C02 extensions by David Banks and Ed Spittles
+
+==========
+6502 Core
+==========
+
+Arlet's original 6502 core (cpu.v) is unchanged.
+
+Note: the 6502/65C02 cores assumes a synchronous memory. This means
+that valid data (DI) is expected on the cycle *after* valid
+address. This allows direct connection to (Xilinx) block RAMs. When
+using asynchronous memory, I suggest registering the address/control
+lines for glitchless output signals.
 
 Have fun. 
+
+==========
+65C02 Core
+==========
+
+A second core (cpu_65c02.v) has been added, based on Arlet's 6502
+core, with additional 65C02 instructions and addressing modes:
+- PHX, PHY, PLX, PLY
+- BRA
+- INC A, DEC A
+- (zp) addressing mode
+- STZ
+- BIT zpx, absx, imm
+- TSB/TRB
+- JMP (,X)
+- NOPs (optional)
+- 65C02 BCD N/Z flags (optional, disabled)
+
+The Rockwell/WDC specific instructions (RMB/SMB/BBR/BBS/WAI/STP) are
+not currently implemented
+
+The 65C02 core passes the Dormann 6502 test suite, and also passes the
+Dormann 65C02 test suite if the optional support for NOPs and 65C02
+BCD flags is enabled.
+
+It has been tested as a BBC Micro "Matchbox" 65C02 Co Processor, in a
+XC6SLX9-2 FPGA, running at 80MHz using 64KB of internel block RAM. It
+just meets timing at 80MHz in this environment. It successfully runs
+BBC Basic IV and Tube Elite.
+
+============
+Known Issues
+============
+
+The Matchbox Co Processor needed one wait state (via RDY) to be added
+to each ROM access (only needed early in the boot process, as
+eventually everything runs from RAM). The DIHOLD logic did not work
+correctly with a single wait state, and so has been commented out.
+
+I now believe the correct fix is actually just:
+
+always @(posedge clk )
+    if( RDY )
+        DIHOLD <= DI;
+ 
+assign DIMUX = ~RDY ? DIHOLD : DI;
diff --git a/cpu_65c02.v b/cpu_65c02.v
index 832acd8..a0f0c73 100644
--- a/cpu_65c02.v
+++ b/cpu_65c02.v
@@ -1,11 +1,21 @@
 /*
- * verilog model of 6502 CPU.
+ * verilog model of 65C02 CPU.
  *
+ * Based on original 6502 "Arlet 6502 Core" by Arlet Ottens 
+ * 
  * (C) Arlet Ottens, <arlet@c-scape.nl>
  *
  * Feel free to use this code in any project (commercial or not), as long as you
  * keep this message, and the copyright notice. This code is provided "as is", 
- * without any warranties of any kind. 
+ * without any warranties of any kind.
+ * 
+ * Support for 65C02 instructions and addressing modes by David Banks and Ed Spittles
+ *
+ * (C) 2016 David Banks and Ed Spittles
+ * 
+ * Feel free to use this code in any project (commercial or not), as long as you
+ * keep this message, and the copyright notice. This code is provided "as is", 
+ * without any warranties of any kind.
  * 
  */