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Added RDY term to AB Hold update

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Arlet
2011-10-08 17:52:03 +02:00
parent 6796444f2c
commit a89c839d29
1 changed files with 1 additions and 1 deletions
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2
cpu.v
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@@ -411,7 +411,7 @@ always @*
* source of the address, such as the ALU or DI. * source of the address, such as the ALU or DI.
*/ */
always @(posedge clk) always @(posedge clk)
if( state != PUSH0 && state != PUSH1 && if( state != PUSH0 && state != PUSH1 && RDY &&
state != PULL0 && state != PULL1 && state != PULL2 ) state != PULL0 && state != PULL1 && state != PULL2 )
begin begin
ABL <= AB[7:0]; ABL <= AB[7:0];