Added RDY term to AB Hold update

2011-10-08 17:52:03 +02:00
parent 6796444f2c
commit a89c839d29
1 changed files with 1 additions and 1 deletions
--- a/cpu.v
+++ b/cpu.v
@@ -411,7 +411,7 @@ always @*
 * source of the address, such as the ALU or DI.
 */
 always @(posedge clk)
-    if( state != PUSH0 && state != PUSH1 &&
+    if( state != PUSH0 && state != PUSH1 && RDY && 
 	state != PULL0 && state != PULL1 && state != PULL2 )
    begin
 	ABL <= AB[7:0];