From ae653ab68868ba9454a05aa571a8c6c5c6aea418 Mon Sep 17 00:00:00 2001
From: Arlet Ottens <arlet@c-scape.nl>
Date: Mon, 31 Aug 2015 20:25:47 +0200
Subject: [PATCH] Added clarification of memory interface

---
 README | 6 +++++-
 cpu.v  | 2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/README b/README
index f851bde..3de3c7c 100644
--- a/README
+++ b/README
@@ -1,4 +1,8 @@
 A Verilog HDL version of the old MOS 6502 CPU.
 
-Have fun. 
+Note: the 6502 core assumes a synchronous memory. This means that valid
+data (DI) is expected on the cycle *after* valid address. This allows
+direct connection to (Xilinx) block RAMs. When using asynchronous memory,
+I suggest registering the address/control lines for glitchless output signals.
 
+Have fun. 
diff --git a/cpu.v b/cpu.v
index 6081128..a08804f 100644
--- a/cpu.v
+++ b/cpu.v
@@ -674,7 +674,6 @@ always @*
 always @*
     case( state )
          BRA1,
-         JSR1,
          RTS1,
          RTI0,
          RTI1,
@@ -683,6 +682,7 @@ always @*
          READ,
          REG,
          JSR0,
+         JSR1,
          JSR2,
          BRK0,
          BRK1,