Added clarification of memory interface

2015-08-31 20:25:47 +02:00
parent dff3abaaac
commit ae653ab688
2 changed files with 6 additions and 2 deletions
--- a/6
+++ b/6
@@ -1,4 +1,8 @@
 A Verilog HDL version of the old MOS 6502 CPU.

-Have fun. 
+Note: the 6502 core assumes a synchronous memory. This means that valid
+data (DI) is expected on the cycle *after* valid address. This allows
+direct connection to (Xilinx) block RAMs. When using asynchronous memory,
+I suggest registering the address/control lines for glitchless output signals.

+Have fun. 
--- a/cpu.v
+++ b/cpu.v
@@ -674,7 +674,6 @@ always @*
 always @*
    case( state )
         BRA1,
-         JSR1,
         RTS1,
         RTI0,
         RTI1,
@@ -683,6 +682,7 @@ always @*
         READ,
         REG,
         JSR0,
+         JSR1,
         JSR2,
         BRK0,
         BRK1,