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Fixed 'load_reg' for CLC/SEC/CLI/SEI/CLV/CLD/SED

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Arlet
2011-09-27 07:11:13 +02:00
parent c51aa17b6b
commit b1472bfe31
1 changed files with 4 additions and 2 deletions
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6
cpu.v
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@@ -975,8 +975,10 @@ always @(posedge clk)
if( state == DECODE && RDY ) if( state == DECODE && RDY )
casex( IR ) casex( IR )
8'b0xxx_xx01, // ORA, AND, EOR, ADC 8'b0xxx_xx01, // ORA, AND, EOR, ADC
8'b1x1x_xx01, // LDA, SBC 8'b1x1x_xx01, // LDA, SBC
8'bxxxx_10x0, // ASLA, ROLA, LSRA, RORA, Txx, DEX, NOP, 8'bxxxx_1010, // ASLA, ROLA, LSRA, RORA, T[XS][SX], DEX, NOP,
8'bxxx0_1000, // PHP, PLP, PHA, PLA, DEY, TAY, INY, INX
8'b1001_1000, // TYA
8'b1011_x1x0, // LDX/LDY 8'b1011_x1x0, // LDX/LDY
8'b1010_xxx0: // LDA/LDX/LDY 8'b1010_xxx0: // LDA/LDX/LDY
load_reg <= 1; load_reg <= 1;