third-party/verilog-6502
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Fixed '=' back to '<=' for 'backwards' signal.

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Arlet
2011-06-08 06:54:11 +02:00
parent e54964f9dd
commit c51aa17b6b
1 changed files with 1 additions and 1 deletions
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cpu.v
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@@ -620,7 +620,7 @@ always @*
always @(posedge clk) always @(posedge clk)
if( RDY ) if( RDY )
backwards = DIMUX[7]; backwards <= DIMUX[7];
/* /*
* ALU A Input MUX * ALU A Input MUX