Arlet 65C02 WIP: Implement JMP (,X)
Change-Id: I4a216b446ae23e05138d574875dbe54cccc052eb
This commit is contained in:
25
cpu_65c02.v
25
cpu_65c02.v
@@ -225,7 +225,10 @@ parameter
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ZP0 = 6'd47, // Z-page - fetch ZP address
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ZP0 = 6'd47, // Z-page - fetch ZP address
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ZPX0 = 6'd48, // ZP, X - fetch ZP, and send to ALU (+X)
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ZPX0 = 6'd48, // ZP, X - fetch ZP, and send to ALU (+X)
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ZPX1 = 6'd49, // ZP, X - load from memory
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ZPX1 = 6'd49, // ZP, X - load from memory
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IND0 = 6'd50; // (ZP) - fetch ZP address, and send to ALU (+0)
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IND0 = 6'd50, // (ZP) - fetch ZP address, and send to ALU (+0)
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JMPIX0 = 6'd51, // JMP (,X)- fetch LSB and send to ALU (+X)
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JMPIX1 = 6'd52, // JMP (,X)- fetch MSB and send to ALU (+Carry)
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JMPIX2 = 6'd53; // JMP (,X)- Wait for ALU (only if needed)
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`ifdef SIM
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`ifdef SIM
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@@ -287,6 +290,10 @@ always @*
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JMP1: statename = "JMP1";
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JMP1: statename = "JMP1";
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JMPI0: statename = "JMPI0";
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JMPI0: statename = "JMPI0";
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JMPI1: statename = "JMPI1";
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JMPI1: statename = "JMPI1";
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JMPIX0: statename = "JMPIX0";
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JMPIX1: statename = "JMPIX1";
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JMPIX2: statename = "JMPIX2";
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endcase
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endcase
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//always @( PC )
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//always @( PC )
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@@ -310,12 +317,14 @@ always @*
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JMP1,
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JMP1,
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JMPI1,
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JMPI1,
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JMPIX1,
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JSR3,
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JSR3,
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RTS3,
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RTS3,
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RTI4: PC_temp = { DIMUX, ADD };
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RTI4: PC_temp = { DIMUX, ADD };
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BRA1: PC_temp = { ABH, ADD };
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BRA1: PC_temp = { ABH, ADD };
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JMPIX2,
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BRA2: PC_temp = { ADD, PCL };
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BRA2: PC_temp = { ADD, PCL };
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BRK2: PC_temp = res ? 16'hfffc :
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BRK2: PC_temp = res ? 16'hfffc :
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@@ -335,6 +344,8 @@ always @*
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PC_inc = 1;
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PC_inc = 1;
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ABS0,
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ABS0,
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JMPIX0,
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JMPIX2,
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ABSX0,
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ABSX0,
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FETCH,
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FETCH,
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BRA0,
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BRA0,
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@@ -345,6 +356,8 @@ always @*
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RTI4,
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RTI4,
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RTS3: PC_inc = 1;
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RTS3: PC_inc = 1;
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JMPIX1: PC_inc = ~CO; // Don't increment PC if we are going to go through JMPIX2
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BRA1: PC_inc = CO ^~ backwards;
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BRA1: PC_inc = CO ^~ backwards;
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default: PC_inc = 0;
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default: PC_inc = 0;
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@@ -367,6 +380,7 @@ parameter
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always @*
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always @*
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case( state )
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case( state )
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JMPIX1,
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ABSX1,
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ABSX1,
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INDX3,
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INDX3,
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INDY2,
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INDY2,
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@@ -377,6 +391,7 @@ always @*
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BRA2,
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BRA2,
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INDY3,
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INDY3,
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JMPIX2,
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ABSX2: AB = { ADD, ABL };
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ABSX2: AB = { ADD, ABL };
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BRA1: AB = { ABH, ADD };
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BRA1: AB = { ABH, ADD };
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@@ -549,6 +564,7 @@ always @*
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INDY1,
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INDY1,
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INDX0,
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INDX0,
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ZPX0,
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ZPX0,
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JMPIX0,
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ABSX0 : regsel = index_y ? SEL_Y : SEL_X;
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ABSX0 : regsel = index_y ? SEL_Y : SEL_X;
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@@ -649,6 +665,7 @@ always @*
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REG,
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REG,
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ZPX0,
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ZPX0,
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INDX0,
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INDX0,
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JMPIX0,
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ABSX0,
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ABSX0,
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RTI0,
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RTI0,
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RTS0,
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RTS0,
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@@ -716,6 +733,7 @@ always @*
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case( state )
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case( state )
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INDY2,
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INDY2,
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BRA1,
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BRA1,
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JMPIX1,
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ABSX1: CI = CO;
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ABSX1: CI = CO;
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DECODE,
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DECODE,
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@@ -896,6 +914,7 @@ always @(posedge clk or posedge reset)
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8'b0100_1100: state <= JMP0;
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8'b0100_1100: state <= JMP0;
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8'b0110_0000: state <= RTS0;
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8'b0110_0000: state <= RTS0;
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8'b0110_1100: state <= JMPI0;
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8'b0110_1100: state <= JMPI0;
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8'b0111_1100: state <= JMPIX0;
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8'b0x00_1000: state <= PUSH0;
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8'b0x00_1000: state <= PUSH0;
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8'b0x10_1000: state <= PULL0;
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8'b0x10_1000: state <= PULL0;
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8'b0xx1_1000: state <= REG; // CLC, SEC, CLI, SEI
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8'b0xx1_1000: state <= REG; // CLC, SEC, CLI, SEI
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@@ -936,6 +955,10 @@ always @(posedge clk or posedge reset)
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ABSX1 : state <= (CO | store | write_back) ? ABSX2 : FETCH;
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ABSX1 : state <= (CO | store | write_back) ? ABSX2 : FETCH;
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ABSX2 : state <= write_back ? READ : FETCH;
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ABSX2 : state <= write_back ? READ : FETCH;
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JMPIX0 : state <= JMPIX1;
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JMPIX1 : state <= CO ? JMPIX2 : JMP0;
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JMPIX2 : state <= JMP0;
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IND0 : state <= INDX1;
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IND0 : state <= INDX1;
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INDX0 : state <= INDX1;
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INDX0 : state <= INDX1;
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