diff --git a/README b/README.md
similarity index 81%
rename from README
rename to README.md
index 3de3c7c..67256ce 100644
--- a/README
+++ b/README.md
@@ -5,4 +5,6 @@ data (DI) is expected on the cycle *after* valid address. This allows
 direct connection to (Xilinx) block RAMs. When using asynchronous memory,
 I suggest registering the address/control lines for glitchless output signals.
 
+[Also check out my new 65C02 project](https://github.com/Arlet/verilog-65c02)
+
 Have fun.