From e6f361d7644f6b994165c3839910022bc3d0fa9a Mon Sep 17 00:00:00 2001 From: Arlet Ottens Date: Wed, 21 Oct 2020 12:12:56 +0200 Subject: [PATCH] Updated README --- README => README.md | 2 ++ 1 file changed, 2 insertions(+) rename README => README.md (81%) diff --git a/README b/README.md similarity index 81% rename from README rename to README.md index 3de3c7c..67256ce 100644 --- a/README +++ b/README.md @@ -5,4 +5,6 @@ data (DI) is expected on the cycle *after* valid address. This allows direct connection to (Xilinx) block RAMs. When using asynchronous memory, I suggest registering the address/control lines for glitchless output signals. +[Also check out my new 65C02 project](https://github.com/Arlet/verilog-65c02) + Have fun.