68 lines
1.9 KiB
Plaintext
68 lines
1.9 KiB
Plaintext
========================================================
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A Verilog HDL version of the old MOS 6502 and 65C02 CPUs
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========================================================
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Original 6502 core by Arlet Ottens
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65C02 extensions by David Banks and Ed Spittles
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==========
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6502 Core
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==========
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Arlet's original 6502 core (cpu.v) is unchanged.
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Note: the 6502/65C02 cores assumes a synchronous memory. This means
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that valid data (DI) is expected on the cycle *after* valid
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address. This allows direct connection to (Xilinx) block RAMs. When
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using asynchronous memory, I suggest registering the address/control
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lines for glitchless output signals.
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Have fun.
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==========
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65C02 Core
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==========
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A second core (cpu_65c02.v) has been added, based on Arlet's 6502
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core, with additional 65C02 instructions and addressing modes:
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- PHX, PHY, PLX, PLY
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- BRA
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- INC A, DEC A
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- (zp) addressing mode
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- STZ
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- BIT zpx, absx, imm
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- TSB/TRB
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- JMP (,X)
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- NOPs (optional)
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- 65C02 BCD N/Z flags (optional, disabled)
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The Rockwell/WDC specific instructions (RMB/SMB/BBR/BBS/WAI/STP) are
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not currently implemented
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The 65C02 core passes the Dormann 6502 test suite, and also passes the
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Dormann 65C02 test suite if the optional support for NOPs and 65C02
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BCD flags is enabled.
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It has been tested as a BBC Micro "Matchbox" 65C02 Co Processor, in a
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XC6SLX9-2 FPGA, running at 80MHz using 64KB of internel block RAM. It
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just meets timing at 80MHz in this environment. It successfully runs
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BBC Basic IV and Tube Elite.
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============
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Known Issues
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============
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The Matchbox Co Processor needed one wait state (via RDY) to be added
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to each ROM access (only needed early in the boot process, as
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eventually everything runs from RAM). The DIHOLD logic did not work
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correctly with a single wait state, and so has been commented out.
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I now believe the correct fix is actually just:
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always @(posedge clk )
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if( RDY )
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DIHOLD <= DI;
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assign DIMUX = ~RDY ? DIHOLD : DI;
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