"updt"
This commit is contained in:
Arnav Sacheti
4
src/peakrdl_busdecoder/cpuif/apb4/__init__.py
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4
src/peakrdl_busdecoder/cpuif/apb4/__init__.py
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from .apb4_cpuif import APB4Cpuif
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from .apb4_cpuif_flat import APB4CpuifFlat
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__all__ = ["APB4Cpuif", "APB4CpuifFlat"]
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81
src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py
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81
src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py
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from systemrdl.node import AddressableNode
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from ..base_cpuif import BaseCpuif
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class APB4Cpuif(BaseCpuif):
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template_path = "apb4_tmpl.sv"
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is_interface = True
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def _port_declaration(self, child: AddressableNode) -> str:
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base = f"apb4_intf.master m_apb_{child.inst_name}"
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if not child.is_array:
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return base
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if child.current_idx is not None:
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return f"{base}_{'_'.join(map(str, child.current_idx))} [N_{child.inst_name.upper()}S]"
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return f"{base} [N_{child.inst_name.upper()}S]"
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@property
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def port_declaration(self) -> str:
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"""Returns the port declaration for the APB4 interface."""
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slave_ports: list[str] = ["apb4_intf.slave s_apb"]
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master_ports: list[str] = list(
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map(self._port_declaration, self.addressable_children)
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)
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return ",\n".join(slave_ports + master_ports)
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def signal(
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self,
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signal: str,
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node: AddressableNode | None = None,
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idx: str | int | None = None,
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) -> str:
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"""Returns the signal name for the given signal and node."""
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if node is None:
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# Node is none, so this is a slave signal
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return f"s_apb.{signal}"
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# Master signal
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base = f"m_apb_{node.inst_name}"
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if not node.is_array:
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return f"{base}.{signal}"
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if node.current_idx is not None:
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# This is a specific instance of an array
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return f"{base}_{'_'.join(map(str, node.current_idx))}.{signal}"
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if idx is not None:
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return f"{base}[{idx}].{signal}"
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raise ValueError("Must provide an index for arrayed interface signals")
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def get_address_predicate(self, node: AddressableNode) -> str:
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"""
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Returns a SystemVerilog expression that evaluates to true when the
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address on the bus matches the address range of the given node.
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"""
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addr_mask = (1 << self.addr_width) - 1
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addr = node.absolute_address & addr_mask
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size = node.size
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if size == 0:
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raise ValueError("Node size must be greater than 0")
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if (addr % size) != 0:
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raise ValueError("Node address must be aligned to its size")
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# Calculate the address range of the node
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addr_start = addr
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addr_end = addr + size - 1
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if addr_end > addr_mask:
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raise ValueError("Node address range exceeds address width")
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if addr_start == addr_end:
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return f"({self.signal('PADDR')} == 'h{addr_start:X})"
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return f"({self.signal('PADDR')} >= 'h{addr_start:X} && {self.signal('PADDR')} <= 'h{addr_end:X})"
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def get_address_decode_condition(self, node: AddressableNode) -> str:
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"""
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Returns a SystemVerilog expression that evaluates to true when the
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address on the bus matches the address range of the given node.
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"""
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addr_pred = self.get_address_predicate(node)
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return addr_pred
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66
src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py
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66
src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py
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from systemrdl.node import AddressableNode
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from ..base_cpuif import BaseCpuif
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class APB4CpuifFlat(BaseCpuif):
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template_path = "apb4_tmpl.sv"
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is_interface = False
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def _port_declaration(self, child: AddressableNode) -> list[str]:
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return [
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f"input logic {self.signal('PCLK', child)}",
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f"input logic {self.signal('PRESETn', child)}",
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f"input logic {self.signal('PSELx', child)}",
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f"input logic {self.signal('PENABLE', child)}",
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f"input logic {self.signal('PWRITE', child)}",
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f"input logic [{self.addr_width - 1}:0] {self.signal('PADDR', child)}",
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f"input logic [2:0] {self.signal('PPROT', child)}",
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f"input logic [{self.data_width - 1}:0] {self.signal('PWDATA', child)}",
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f"input logic [{self.data_width // 8 - 1}:0] {self.signal('PSTRB', child)}",
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f"output logic [{self.data_width - 1}:0] {self.signal('PRDATA', child)}",
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f"output logic {self.signal('PREADY', child)}",
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f"output logic {self.signal('PSLVERR', child)}",
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]
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@property
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def port_declaration(self) -> str:
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slave_ports: list[str] = [
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f"input logic {self.signal('PCLK')}",
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f"input logic {self.signal('PRESETn')}",
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f"input logic {self.signal('PSELx')}",
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f"input logic {self.signal('PENABLE')}",
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f"input logic {self.signal('PWRITE')}",
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f"input logic [{self.addr_width - 1}:0] {self.signal('PADDR')}",
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f"input logic [2:0] {self.signal('PPROT')}",
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f"input logic [{self.data_width - 1}:0] {self.signal('PWDATA')}",
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f"input logic [{self.data_width // 8 - 1}:0] {self.signal('PSTRB')}",
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f"output logic [{self.data_width - 1}:0] {self.signal('PRDATA')}",
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f"output logic {self.signal('PREADY')}",
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f"output logic {self.signal('PSLVERR')}",
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]
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master_ports: list[str] = []
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for child in self.addressable_children:
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master_ports.extend(self._port_declaration(child))
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return ",\n".join(slave_ports + master_ports)
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def signal(
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self,
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signal: str,
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node: AddressableNode | None = None,
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idx: str | int | None = None,
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) -> str:
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if node is None:
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# Node is none, so this is a slave signal
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return f"s_apb_{signal}"
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# Master signal
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base = f"m_apb_{node.inst_name}"
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if not node.is_array:
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return f"{base}_{signal}"
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if node.current_idx is not None:
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# This is a specific instance of an array
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return f"{base}_{signal}_{'_'.join(map(str, node.current_idx))}"
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if idx is not None:
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return f"{base}_{signal}[{idx}]"
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return f"{base}_{signal}[N_{node.inst_name.upper()}S]"
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119
src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
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119
src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
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@@ -0,0 +1,119 @@
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{%- if cpuif.is_interface -%}
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`ifndef SYNTHESIS
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initial begin
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assert_bad_addr_width: assert($bits({{cpuif.signal("PADDR")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
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else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("PADDR")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
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assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
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else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
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end
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`endif
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{% endif -%}
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//======================================================
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// APB Fanout
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//======================================================
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{%- for child in cpuif.addressable_children -%}
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{%- if child is array -%}
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for (genvar g_{{child.inst_name|lower}}_idx = 0; g_{{child.inst_name|lower}}_idx < N_{{child.inst_name|upper}}S; g_{{child.inst_name|lower}}_idx++) begin : g_passthrough_{{child.inst_name|lower}}
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assign {{self.signal("PCLK", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PCLK")}};
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assign {{self.signal("PRESETn", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PRESETn")}};
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assign {{self.signal("PENABLE", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PENABLE")}};
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assign {{self.signal("PWRITE", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PWRITE")}};
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assign {{self.signal("PADDR", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PADDR")}} [{{child.addr_width - 1}}:0]; // FIXME: Check slicing
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assign {{self.signal("PPROT", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PPROT")}};
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assign {{self.signal("PWDATA", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PWDATA")}};
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assign {{self.signal("PSTRB", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PSTRB")}};
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end
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{%- else -%}
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assign {{self.signal("PCLK", child)}} = {{self.signal("PCLK")}};
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assign {{self.signal("PRESETn", child)}} = {{self.signal("PRESETn")}};
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assign {{self.signal("PENABLE", child)}} = {{self.signal("PENABLE")}};
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assign {{self.signal("PWRITE", child)}} = {{self.signal("PWRITE")}};
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assign {{self.signal("PADDR", child)}} = {{self.signal("PADDR")}} [{{child.addr_width - 1}}:0]; // FIXME: Check slicing
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assign {{self.signal("PPROT", child)}} = {{self.signal("PPROT")}};
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assign {{self.signal("PWDATA", child)}} = {{self.signal("PWDATA")}};
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assign {{self.signal("PSTRB", child)}} = {{self.signal("PSTRB")}};
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{%- endif -%}
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{%- endfor -%}
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//======================================================
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// Address Decode Logic
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//======================================================
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always_comb begin
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// Default all PSELx signals to 0
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{%- for child in cpuif.addressable_children -%}
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{%- if child is array -%}
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for (int {{child.inst_name|lower}}_idx = 0; {{child.inst_name|lower}}_idx < N_{{child.inst_name|upper}}S; {{child.inst_name|lower}}_idx++) begin
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{{self.signal("PSELx", child, f"{child.inst_name.lower()}_idx")}} = 1'b0;
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end
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{%- else -%}
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{{self.signal("PSELx", child)}} = 1'b0;
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{%- endif -%}
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{%- endfor -%}
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if ({{self.signal("PSELx")}}) begin
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{%- for child in cpuif.addressable_children -%}
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{%- if loop.first -%}
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if ({{cpuif.get_address_decode_condition(child)}}) begin
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{%- else -%}
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end else if ({{cpuif.get_address_decode_condition(child)}}) begin
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{%- endif -%}
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// Address matched for {{child.inst_name}}
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{%- if child is array -%}
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for (genvar {{child.inst_name|lower}}_idx = 0; {{child.inst_name|lower}}_idx < N_{{child.inst_name|upper}}S; {{child.inst_name|lower}}_idx++) begin
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{{self.signal("PSELx", child, f"{child.inst_name.lower()}_idx")}} = 1'b1;
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end
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{%- else -%}
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{{self.signal("PSELx", child)}} = 1'b1;
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{%- endif -%}
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{%- if loop.last -%}
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end else begin
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// No address matched
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{%- endif -%}
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{%- endfor -%}
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end
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end else begin
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// PSELx is low, nothing to do
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end
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end
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//======================================================
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// Read Data Mux
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//======================================================
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always_comb begin
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// Default read data to 0
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{{self.signal("PRDATA")}} = '0;
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{{self.signal("PREADY")}} = 1'b1;
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{{self.signal("PSLVERR")}} = 1'b0;
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if ({{self.signal("PSELx")}} && !{{self.signal("PWRITE")}} && {{self.signal("PENABLE")}}) begin
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{%- for child in cpuif.addressable_children -%}
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{%- if loop.first -%}
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if ({{cpuif.get_address_decode_condition(child)}}) begin
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{%- else -%}
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end else if ({{cpuif.get_address_decode_condition(child)}}) begin
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{%- endif -%}
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// Address matched for {{child.inst_name}}
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{%- if child is array -%}
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for (genvar {{child.inst_name|lower}}_idx = 0; {{child.inst_name|lower}}_idx < N_{{child.inst_name|upper}}S; {{child.inst_name|lower}}_idx++) begin
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{{self.signal("PRDATA")}} = {{self.signal("PRDATA", child, f"{child.inst_name.lower()}_idx")}};
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{{self.signal("PREADY")}} = {{self.signal("PREADY", child, f"{child.inst_name.lower()}_idx")}};
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{{self.signal("PSLVERR")}} = {{self.signal("PSLVERR", child, f"{child.inst_name.lower()}_idx")}};
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end
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{%- else -%}
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{{self.signal("PRDATA")}} = {{self.signal("PRDATA", child)}};
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{{self.signal("PREADY")}} = {{self.signal("PREADY", child)}};
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{{self.signal("PSLVERR")}} = {{self.signal("PSLVERR", child)}};
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{%- endif -%}
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{%- if loop.last -%}
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end else begin
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// No address matched
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{{self.signal("PRDATA")}} = {'hdeadbeef}[{{ds.data_width - 1}}:0]; // Indicate error on no match
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{{self.signal("PSLVERR")}} = 1'b1; // Indicate error on no match
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end
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{%- endif -%}
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{%- endfor -%}
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end else begin
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// Not a read transfer, nothing to do
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end
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end
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