"updt"
This commit is contained in:
Arnav Sacheti
67
src/peakrdl_busdecoder/cpuif/axi4lite/__init__.py
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67
src/peakrdl_busdecoder/cpuif/axi4lite/__init__.py
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from ..base_cpuif import CpuifBase
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class AXI4Lite_Cpuif(CpuifBase):
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template_path = "axi4lite_tmpl.sv"
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is_interface = True
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@property
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def port_declaration(self) -> str:
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return "axi4lite_intf.slave s_axil"
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def signal(self, name: str) -> str:
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return "s_axil." + name.upper()
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@property
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def busdecoder_latency(self) -> int:
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return max(self.exp.ds.min_read_latency, self.exp.ds.min_write_latency)
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@property
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def max_outstanding(self) -> int:
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"""
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Best pipelined performance is when the max outstanding transactions
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is the design's latency + 2.
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Anything beyond that does not have any effect, aside from adding unnecessary
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logic and additional buffer-bloat latency.
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"""
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return self.busdecoder_latency + 2
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@property
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def resp_buffer_size(self) -> int:
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"""
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Response buffer size must be greater or equal to max outstanding
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transactions to prevent response overrun.
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"""
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return self.max_outstanding
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class AXI4Lite_Cpuif_flattened(AXI4Lite_Cpuif):
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is_interface = False
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@property
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def port_declaration(self) -> str:
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lines = [
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"output logic " + self.signal("awready"),
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"input wire " + self.signal("awvalid"),
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f"input wire [{self.addr_width - 1}:0] " + self.signal("awaddr"),
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"input wire [2:0] " + self.signal("awprot"),
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"output logic " + self.signal("wready"),
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"input wire " + self.signal("wvalid"),
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f"input wire [{self.data_width - 1}:0] " + self.signal("wdata"),
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f"input wire [{self.data_width_bytes - 1}:0]" + self.signal("wstrb"),
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"input wire " + self.signal("bready"),
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"output logic " + self.signal("bvalid"),
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"output logic [1:0] " + self.signal("bresp"),
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"output logic " + self.signal("arready"),
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"input wire " + self.signal("arvalid"),
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f"input wire [{self.addr_width - 1}:0] " + self.signal("araddr"),
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"input wire [2:0] " + self.signal("arprot"),
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"input wire " + self.signal("rready"),
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"output logic " + self.signal("rvalid"),
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f"output logic [{self.data_width - 1}:0] " + self.signal("rdata"),
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"output logic [1:0] " + self.signal("rresp"),
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]
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return ",\n".join(lines)
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def signal(self, name: str) -> str:
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return "s_axil_" + name
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254
src/peakrdl_busdecoder/cpuif/axi4lite/axi4lite_tmpl.sv
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254
src/peakrdl_busdecoder/cpuif/axi4lite/axi4lite_tmpl.sv
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@@ -0,0 +1,254 @@
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{%- if cpuif.is_interface -%}
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`ifndef SYNTHESIS
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initial begin
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assert_bad_addr_width: assert($bits({{cpuif.signal("araddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
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else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("araddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
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assert_bad_data_width: assert($bits({{cpuif.signal("wdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
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else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("wdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
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end
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`endif
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{% endif -%}
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// Max Outstanding Transactions: {{cpuif.max_outstanding}}
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logic [{{clog2(cpuif.max_outstanding+1)-1}}:0] axil_n_in_flight;
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logic axil_prev_was_rd;
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logic axil_arvalid;
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logic [{{cpuif.addr_width-1}}:0] axil_araddr;
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logic axil_ar_accept;
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logic axil_awvalid;
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logic [{{cpuif.addr_width-1}}:0] axil_awaddr;
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logic axil_wvalid;
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logic [{{cpuif.data_width-1}}:0] axil_wdata;
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logic [{{cpuif.data_width_bytes-1}}:0] axil_wstrb;
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logic axil_aw_accept;
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logic axil_resp_acked;
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// Transaction request acceptance
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always_ff {{get_always_ff_event(cpuif.reset)}} begin
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if({{get_resetsignal(cpuif.reset)}}) begin
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axil_prev_was_rd <= '0;
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axil_arvalid <= '0;
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axil_araddr <= '0;
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axil_awvalid <= '0;
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axil_awaddr <= '0;
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axil_wvalid <= '0;
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axil_wdata <= '0;
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axil_wstrb <= '0;
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axil_n_in_flight <= '0;
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end else begin
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// AR* acceptance register
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if(axil_ar_accept) begin
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axil_prev_was_rd <= '1;
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axil_arvalid <= '0;
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end
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if({{cpuif.signal("arvalid")}} && {{cpuif.signal("arready")}}) begin
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axil_arvalid <= '1;
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axil_araddr <= {{cpuif.signal("araddr")}};
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end
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// AW* & W* acceptance registers
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if(axil_aw_accept) begin
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axil_prev_was_rd <= '0;
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axil_awvalid <= '0;
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axil_wvalid <= '0;
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end
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if({{cpuif.signal("awvalid")}} && {{cpuif.signal("awready")}}) begin
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axil_awvalid <= '1;
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axil_awaddr <= {{cpuif.signal("awaddr")}};
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end
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if({{cpuif.signal("wvalid")}} && {{cpuif.signal("wready")}}) begin
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axil_wvalid <= '1;
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axil_wdata <= {{cpuif.signal("wdata")}};
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axil_wstrb <= {{cpuif.signal("wstrb")}};
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end
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// Keep track of in-flight transactions
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if((axil_ar_accept || axil_aw_accept) && !axil_resp_acked) begin
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axil_n_in_flight <= axil_n_in_flight + 1'b1;
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end else if(!(axil_ar_accept || axil_aw_accept) && axil_resp_acked) begin
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axil_n_in_flight <= axil_n_in_flight - 1'b1;
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end
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end
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end
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always_comb begin
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{{cpuif.signal("arready")}} = (!axil_arvalid || axil_ar_accept);
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{{cpuif.signal("awready")}} = (!axil_awvalid || axil_aw_accept);
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{{cpuif.signal("wready")}} = (!axil_wvalid || axil_aw_accept);
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end
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// Request dispatch
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always_comb begin
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cpuif_wr_data = axil_wdata;
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for(int i=0; i<{{cpuif.data_width_bytes}}; i++) begin
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cpuif_wr_biten[i*8 +: 8] = {8{axil_wstrb[i]}};
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end
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cpuif_req = '0;
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cpuif_req_is_wr = '0;
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cpuif_addr = '0;
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axil_ar_accept = '0;
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axil_aw_accept = '0;
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if(axil_n_in_flight < {{clog2(cpuif.max_outstanding+1)}}'d{{cpuif.max_outstanding}}) begin
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// Can safely issue more transactions without overwhelming response buffer
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if(axil_arvalid && !axil_prev_was_rd) begin
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cpuif_req = '1;
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cpuif_req_is_wr = '0;
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{%- if cpuif.data_width_bytes == 1 %}
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cpuif_addr = axil_araddr;
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{%- else %}
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cpuif_addr = {axil_araddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
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{%- endif %}
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if(!cpuif_req_stall_rd) axil_ar_accept = '1;
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end else if(axil_awvalid && axil_wvalid) begin
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cpuif_req = '1;
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cpuif_req_is_wr = '1;
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{%- if cpuif.data_width_bytes == 1 %}
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cpuif_addr = axil_awaddr;
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{%- else %}
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cpuif_addr = {axil_awaddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
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{%- endif %}
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if(!cpuif_req_stall_wr) axil_aw_accept = '1;
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end else if(axil_arvalid) begin
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cpuif_req = '1;
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cpuif_req_is_wr = '0;
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{%- if cpuif.data_width_bytes == 1 %}
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cpuif_addr = axil_araddr;
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{%- else %}
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cpuif_addr = {axil_araddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
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{%- endif %}
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if(!cpuif_req_stall_rd) axil_ar_accept = '1;
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end
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end
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end
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// AXI4-Lite Response Logic
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{%- if cpuif.resp_buffer_size == 1 %}
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always_ff {{get_always_ff_event(cpuif.reset)}} begin
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if({{get_resetsignal(cpuif.reset)}}) begin
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{{cpuif.signal("rvalid")}} <= '0;
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{{cpuif.signal("rresp")}} <= '0;
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{{cpuif.signal("rdata")}} <= '0;
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{{cpuif.signal("bvalid")}} <= '0;
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{{cpuif.signal("bresp")}} <= '0;
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end else begin
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if({{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) begin
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{{cpuif.signal("rvalid")}} <= '0;
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end
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if({{cpuif.signal("bvalid")}} && {{cpuif.signal("bready")}}) begin
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{{cpuif.signal("bvalid")}} <= '0;
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end
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if(cpuif_rd_ack) begin
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{{cpuif.signal("rvalid")}} <= '1;
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{{cpuif.signal("rdata")}} <= cpuif_rd_data;
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if(cpuif_rd_err) {{cpuif.signal("rresp")}} <= 2'b10; // SLVERR
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else {{cpuif.signal("rresp")}} <= 2'b00; // OKAY
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end
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if(cpuif_wr_ack) begin
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{{cpuif.signal("bvalid")}} <= '1;
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if(cpuif_wr_err) {{cpuif.signal("bresp")}} <= 2'b10; // SLVERR
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else {{cpuif.signal("bresp")}} <= 2'b00; // OKAY
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end
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end
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end
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always_comb begin
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axil_resp_acked = '0;
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if({{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) axil_resp_acked = '1;
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if({{cpuif.signal("bvalid")}} && {{cpuif.signal("bready")}}) axil_resp_acked = '1;
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end
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{%- else %}
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struct {
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logic is_wr;
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logic err;
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logic [{{cpuif.data_width-1}}:0] rdata;
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} axil_resp_buffer[{{roundup_pow2(cpuif.resp_buffer_size)}}];
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{%- if not is_pow2(cpuif.resp_buffer_size) %}
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// axil_resp_buffer is intentionally padded to the next power of two despite
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// only requiring {{cpuif.resp_buffer_size}} entries.
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// This is to avoid quirks in some tools that cannot handle indexing into a non-power-of-2 array.
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// Unused entries are expected to be optimized away
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{% endif %}
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logic [{{clog2(cpuif.resp_buffer_size)}}:0] axil_resp_wptr;
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logic [{{clog2(cpuif.resp_buffer_size)}}:0] axil_resp_rptr;
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always_ff {{get_always_ff_event(cpuif.reset)}} begin
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if({{get_resetsignal(cpuif.reset)}}) begin
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for(int i=0; i<{{cpuif.resp_buffer_size}}; i++) begin
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axil_resp_buffer[i].is_wr <= '0;
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axil_resp_buffer[i].err <= '0;
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axil_resp_buffer[i].rdata <= '0;
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end
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axil_resp_wptr <= '0;
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axil_resp_rptr <= '0;
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end else begin
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// Store responses in buffer until AXI response channel accepts them
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if(cpuif_rd_ack || cpuif_wr_ack) begin
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if(cpuif_rd_ack) begin
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axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].is_wr <= '0;
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axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].err <= cpuif_rd_err;
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axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].rdata <= cpuif_rd_data;
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end else if(cpuif_wr_ack) begin
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axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].is_wr <= '1;
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axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].err <= cpuif_wr_err;
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end
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{%- if is_pow2(cpuif.resp_buffer_size) %}
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axil_resp_wptr <= axil_resp_wptr + 1'b1;
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{%- else %}
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if(axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] == {{cpuif.resp_buffer_size-1}}) begin
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axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= '0;
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axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)}}] <= ~axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)}}];
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end else begin
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axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] + 1'b1;
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end
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{%- endif %}
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end
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// Advance read pointer when acknowledged
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if(axil_resp_acked) begin
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{%- if is_pow2(cpuif.resp_buffer_size) %}
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axil_resp_rptr <= axil_resp_rptr + 1'b1;
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{%- else %}
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if(axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] == {{cpuif.resp_buffer_size-1}}) begin
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axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= '0;
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axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)}}] <= ~axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)}}];
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end else begin
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axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] + 1'b1;
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end
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{%- endif %}
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end
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end
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end
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always_comb begin
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axil_resp_acked = '0;
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{{cpuif.signal("bvalid")}} = '0;
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{{cpuif.signal("rvalid")}} = '0;
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if(axil_resp_rptr != axil_resp_wptr) begin
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if(axil_resp_buffer[axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].is_wr) begin
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{{cpuif.signal("bvalid")}} = '1;
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if({{cpuif.signal("bready")}}) axil_resp_acked = '1;
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end else begin
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{{cpuif.signal("rvalid")}} = '1;
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if({{cpuif.signal("rready")}}) axil_resp_acked = '1;
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end
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end
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{{cpuif.signal("rdata")}} = axil_resp_buffer[axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].rdata;
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if(axil_resp_buffer[axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].err) begin
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{{cpuif.signal("bresp")}} = 2'b10;
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{{cpuif.signal("rresp")}} = 2'b10;
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end else begin
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{{cpuif.signal("bresp")}} = 2'b00;
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{{cpuif.signal("rresp")}} = 2'b00;
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end
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end
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{%- endif %}
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