"updt"

src/peakrdl_busdecoder/package_tmpl.sv

@@ -0,0 +1,10 @@
+// Generated by PeakRDL-busdecoder - A free and open-source SystemVerilog generator
+//  https://github.com/SystemRDL/PeakRDL-busdecoder
+
+package {{ds.package_name}};
+
+    localparam {{ds.module_name.upper()}}_DATA_WIDTH = {{ds.cpuif_data_width}};
+    localparam {{ds.module_name.upper()}}_MIN_ADDR_WIDTH = {{ds.addr_width}};
+    localparam {{ds.module_name.upper()}}_SIZE = {{SVInt(ds.top_node.size)}};
+endpackage
+{# (eof newline anchor) #}