Add cocotb testbench for validating generated bus decoder RTL across APB3, APB4, and AXI4-Lite interfaces (#9)
* Initial plan * Add cocotb test infrastructure and testbenches for APB3, APB4, and AXI4-Lite Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add integration tests, examples, and documentation for cocotb testbenches Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Address code review feedback: use relative imports and update installation docs Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add implementation summary document Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Merge cocotb dependencies into test group Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add optional cocotb simulation workflow with Icarus Verilog Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
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Copilot
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tests/cocotb/testbenches/test_apb4_decoder.py
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tests/cocotb/testbenches/test_apb4_decoder.py
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"""Cocotb tests for APB4 bus decoder."""
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import os
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import tempfile
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from pathlib import Path
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import cocotb
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import pytest
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, Timer
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from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
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# Import the common test utilities
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import sys
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sys.path.insert(0, str(Path(__file__).parent.parent))
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from common.utils import compile_rdl_and_export
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# APB4 Master BFM
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class APB4Master:
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"""APB4 Master Bus Functional Model."""
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def __init__(self, dut, name, clock):
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self.dut = dut
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self.clock = clock
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self.name = name
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self.psel = getattr(dut, f"{name}_PSEL")
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self.penable = getattr(dut, f"{name}_PENABLE")
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self.pwrite = getattr(dut, f"{name}_PWRITE")
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self.paddr = getattr(dut, f"{name}_PADDR")
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self.pwdata = getattr(dut, f"{name}_PWDATA")
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self.pstrb = getattr(dut, f"{name}_PSTRB")
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self.pprot = getattr(dut, f"{name}_PPROT")
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self.prdata = getattr(dut, f"{name}_PRDATA")
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self.pready = getattr(dut, f"{name}_PREADY")
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self.pslverr = getattr(dut, f"{name}_PSLVERR")
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def reset(self):
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"""Reset the bus to idle state."""
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self.psel.value = 0
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self.penable.value = 0
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self.pwrite.value = 0
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self.paddr.value = 0
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self.pwdata.value = 0
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self.pstrb.value = 0
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self.pprot.value = 0
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async def write(self, addr, data, strb=None):
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"""Perform APB4 write transaction."""
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if strb is None:
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strb = 0xF
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await RisingEdge(self.clock)
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self.psel.value = 1
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self.penable.value = 0
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self.pwrite.value = 1
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self.paddr.value = addr
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self.pwdata.value = data
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self.pstrb.value = strb
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self.pprot.value = 0
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await RisingEdge(self.clock)
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self.penable.value = 1
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while True:
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await RisingEdge(self.clock)
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if self.pready.value == 1:
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error = self.pslverr.value == 1
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break
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self.psel.value = 0
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self.penable.value = 0
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return not error
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async def read(self, addr):
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"""Perform APB4 read transaction."""
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await RisingEdge(self.clock)
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self.psel.value = 1
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self.penable.value = 0
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self.pwrite.value = 0
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self.paddr.value = addr
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self.pprot.value = 0
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await RisingEdge(self.clock)
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self.penable.value = 1
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while True:
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await RisingEdge(self.clock)
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if self.pready.value == 1:
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data = self.prdata.value.integer
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error = self.pslverr.value == 1
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break
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self.psel.value = 0
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self.penable.value = 0
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return data, error
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# APB4 Slave responder
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class APB4SlaveResponder:
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"""Simple APB4 Slave responder that acknowledges all transactions."""
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def __init__(self, dut, name, clock):
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self.dut = dut
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self.clock = clock
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self.name = name
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self.psel = getattr(dut, f"{name}_PSEL")
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self.penable = getattr(dut, f"{name}_PENABLE")
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self.pwrite = getattr(dut, f"{name}_PWRITE")
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self.paddr = getattr(dut, f"{name}_PADDR")
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self.pwdata = getattr(dut, f"{name}_PWDATA")
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self.pstrb = getattr(dut, f"{name}_PSTRB")
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self.prdata = getattr(dut, f"{name}_PRDATA")
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self.pready = getattr(dut, f"{name}_PREADY")
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self.pslverr = getattr(dut, f"{name}_PSLVERR")
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# Storage for register values
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self.storage = {}
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async def run(self):
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"""Run the slave responder."""
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while True:
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await RisingEdge(self.clock)
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if self.psel.value == 1 and self.penable.value == 1:
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addr = self.paddr.value.integer
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if self.pwrite.value == 1:
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# Write operation
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data = self.pwdata.value.integer
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self.storage[addr] = data
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self.pready.value = 1
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self.pslverr.value = 0
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else:
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# Read operation
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data = self.storage.get(addr, 0)
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self.prdata.value = data
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self.pready.value = 1
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self.pslverr.value = 0
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else:
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self.pready.value = 0
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self.pslverr.value = 0
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@cocotb.test()
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async def test_simple_read_write(dut):
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"""Test simple read and write operations."""
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# Start clock
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clock = Clock(dut.clk, 10, units="ns")
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cocotb.start_soon(clock.start())
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# Create master and slave
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master = APB4Master(dut, "s_apb", dut.clk)
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slave = APB4SlaveResponder(dut, "m_apb_test_reg", dut.clk)
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# Reset
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dut.rst.value = 1
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master.reset()
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await Timer(100, units="ns")
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await RisingEdge(dut.clk)
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dut.rst.value = 0
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await RisingEdge(dut.clk)
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# Start slave responder
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cocotb.start_soon(slave.run())
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# Wait a few cycles
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for _ in range(5):
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await RisingEdge(dut.clk)
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# Write test
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dut._log.info("Writing 0xDEADBEEF to address 0x0")
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success = await master.write(0x0, 0xDEADBEEF)
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assert success, "Write operation failed"
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# Read test
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dut._log.info("Reading from address 0x0")
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data, error = await master.read(0x0)
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assert not error, "Read operation returned error"
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assert data == 0xDEADBEEF, f"Read data mismatch: expected 0xDEADBEEF, got 0x{data:08X}"
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dut._log.info("Test passed!")
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@cocotb.test()
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async def test_multiple_registers(dut):
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"""Test operations on multiple registers."""
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# Start clock
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clock = Clock(dut.clk, 10, units="ns")
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cocotb.start_soon(clock.start())
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# Create master and slaves
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master = APB4Master(dut, "s_apb", dut.clk)
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slave1 = APB4SlaveResponder(dut, "m_apb_reg1", dut.clk)
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slave2 = APB4SlaveResponder(dut, "m_apb_reg2", dut.clk)
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slave3 = APB4SlaveResponder(dut, "m_apb_reg3", dut.clk)
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# Reset
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dut.rst.value = 1
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master.reset()
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await Timer(100, units="ns")
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await RisingEdge(dut.clk)
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dut.rst.value = 0
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await RisingEdge(dut.clk)
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# Start slave responders
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cocotb.start_soon(slave1.run())
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cocotb.start_soon(slave2.run())
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cocotb.start_soon(slave3.run())
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# Wait a few cycles
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for _ in range(5):
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await RisingEdge(dut.clk)
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# Test each register
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test_data = [0x12345678, 0xABCDEF00, 0xCAFEBABE]
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for i, data in enumerate(test_data):
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addr = i * 4
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dut._log.info(f"Writing 0x{data:08X} to address 0x{addr:X}")
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success = await master.write(addr, data)
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assert success, f"Write to address 0x{addr:X} failed"
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dut._log.info(f"Reading from address 0x{addr:X}")
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read_data, error = await master.read(addr)
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assert not error, f"Read from address 0x{addr:X} returned error"
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assert read_data == data, f"Data mismatch at 0x{addr:X}: expected 0x{data:08X}, got 0x{read_data:08X}"
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dut._log.info("Test passed!")
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@cocotb.test()
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async def test_byte_strobe(dut):
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"""Test byte strobe functionality."""
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# Start clock
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clock = Clock(dut.clk, 10, units="ns")
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cocotb.start_soon(clock.start())
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# Create master and slave
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master = APB4Master(dut, "s_apb", dut.clk)
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slave = APB4SlaveResponder(dut, "m_apb_test_reg", dut.clk)
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# Reset
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dut.rst.value = 1
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master.reset()
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await Timer(100, units="ns")
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await RisingEdge(dut.clk)
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dut.rst.value = 0
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await RisingEdge(dut.clk)
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# Start slave responder
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cocotb.start_soon(slave.run())
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# Wait a few cycles
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for _ in range(5):
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await RisingEdge(dut.clk)
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# Write full word
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await master.write(0x0, 0x12345678, strb=0xF)
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# Read back
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data, error = await master.read(0x0)
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assert not error
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assert data == 0x12345678
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# Write only lower byte
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await master.write(0x0, 0x000000AB, strb=0x1)
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data, error = await master.read(0x0)
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assert not error
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assert (data & 0xFF) == 0xAB
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dut._log.info("Test passed!")
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