update tmpl

src/peakrdl_busdecoder/module_tmpl.sv

@@ -1,13 +1,12 @@
-
 //==========================================================
 //  Module: {{ds.module_name}}
 //  Description: CPU Interface Bus Decoder
-//  Author: PeakRDL-busdecoder
+//  Author: PeakRDL-BusDecoder
 //  License: LGPL-3.0
 //  Date: {{current_date}}
 //  Version: {{version}}
 //  Links:
-//    - https://github.com/arnavsacheti/PeakRDL-busdecoder
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
 //==========================================================
 
 
@@ -17,7 +16,6 @@ module {{ds.module_name}}
 ) {%- endif %} (
     {{cpuif.port_declaration|indent(4)}}
 );
-
     //--------------------------------------------------------------------------
     // CPU Bus interface logic
     //--------------------------------------------------------------------------

src/peakrdl_busdecoder/package_tmpl.sv

@@ -1,8 +1,16 @@
-// Generated by PeakRDL-busdecoder - A free and open-source SystemVerilog generator
-//  https://github.com/arnavsacheti/PeakRDL-busdecoder
+//==========================================================
+//  Package: {{ds.package_name}}
+//  Description: CPU Interface Bus Decoder Package
+//  Author: PeakRDL-BusDecoder
+//  License: LGPL-3.0
+//  Date: {{current_date}}
+//  Version: {{version}}
+//  Links:
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
+//==========================================================
+
 
 package {{ds.package_name}};
-
     localparam {{ds.module_name.upper()}}_DATA_WIDTH = {{ds.cpuif_data_width}};
     localparam {{ds.module_name.upper()}}_MIN_ADDR_WIDTH = {{ds.addr_width}};
     localparam {{ds.module_name.upper()}}_SIZE = {{SVInt(ds.top_node.size)}};