Add cocotb testbench for validating generated bus decoder RTL across APB3, APB4, and AXI4-Lite interfaces (#9)
* Initial plan * Add cocotb test infrastructure and testbenches for APB3, APB4, and AXI4-Lite Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add integration tests, examples, and documentation for cocotb testbenches Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Address code review feedback: use relative imports and update installation docs Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add implementation summary document Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Merge cocotb dependencies into test group Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add optional cocotb simulation workflow with Icarus Verilog Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
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Copilot
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tests/cocotb/testbenches/test_apb4_runner.py
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tests/cocotb/testbenches/test_apb4_runner.py
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"""Pytest test runner for APB4 cocotb tests."""
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import os
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import shutil
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import tempfile
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from pathlib import Path
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import pytest
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from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
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# Import the common test utilities
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import sys
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sys.path.insert(0, str(Path(__file__).parent.parent))
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from common.utils import compile_rdl_and_export
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# Check if Icarus Verilog is available
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def is_simulator_available():
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"""Check if Icarus Verilog simulator is available."""
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return shutil.which("iverilog") is not None
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# Skip tests if simulator is not available
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skip_if_no_simulator = pytest.mark.skipif(
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not is_simulator_available(),
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reason="Requires Icarus Verilog or other simulator to be installed"
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)
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def generate_testbench_wrapper(top_name, slave_ports, tmpdir_path):
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"""
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Generate a testbench wrapper that exposes interface signals.
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Args:
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top_name: Name of the top-level module
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slave_ports: List of slave port names
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tmpdir_path: Path to temporary directory
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Returns:
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Path to generated testbench file
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"""
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tb_path = tmpdir_path / f"tb_{top_name}.sv"
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with open(tb_path, "w") as f:
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f.write(f"""
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module tb_{top_name} (
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input logic clk,
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input logic rst
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);
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// Instantiate APB4 interfaces
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apb4_intf #(
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.DATA_WIDTH(32),
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.ADDR_WIDTH(32)
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) s_apb ();
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""")
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# Create interface instances for each slave port
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for port in slave_ports:
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f.write(f"""
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apb4_intf #(
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.DATA_WIDTH(32),
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.ADDR_WIDTH(32)
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) {port} ();
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""")
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# Wire master signals
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f.write("""
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// Wire master signals from interface to top level for cocotb access
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logic s_apb_PSEL;
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logic s_apb_PENABLE;
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logic s_apb_PWRITE;
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logic [31:0] s_apb_PADDR;
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logic [31:0] s_apb_PWDATA;
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logic [3:0] s_apb_PSTRB;
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logic [2:0] s_apb_PPROT;
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logic [31:0] s_apb_PRDATA;
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logic s_apb_PREADY;
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logic s_apb_PSLVERR;
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assign s_apb.PSEL = s_apb_PSEL;
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assign s_apb.PENABLE = s_apb_PENABLE;
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assign s_apb.PWRITE = s_apb_PWRITE;
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assign s_apb.PADDR = s_apb_PADDR;
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assign s_apb.PWDATA = s_apb_PWDATA;
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assign s_apb.PSTRB = s_apb_PSTRB;
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assign s_apb.PPROT = s_apb_PPROT;
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assign s_apb_PRDATA = s_apb.PRDATA;
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assign s_apb_PREADY = s_apb.PREADY;
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assign s_apb_PSLVERR = s_apb.PSLVERR;
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""")
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# Wire slave signals
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for port in slave_ports:
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f.write(f"""
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logic {port}_PSEL;
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logic {port}_PENABLE;
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logic {port}_PWRITE;
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logic [31:0] {port}_PADDR;
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logic [31:0] {port}_PWDATA;
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logic [3:0] {port}_PSTRB;
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logic [31:0] {port}_PRDATA;
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logic {port}_PREADY;
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logic {port}_PSLVERR;
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assign {port}_PSEL = {port}.PSEL;
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assign {port}_PENABLE = {port}.PENABLE;
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assign {port}_PWRITE = {port}.PWRITE;
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assign {port}_PADDR = {port}.PADDR;
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assign {port}_PWDATA = {port}.PWDATA;
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assign {port}_PSTRB = {port}.PSTRB;
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assign {port}.PRDATA = {port}_PRDATA;
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assign {port}.PREADY = {port}_PREADY;
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assign {port}.PSLVERR = {port}_PSLVERR;
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""")
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# Instantiate DUT
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f.write(f"""
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// Instantiate DUT
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{top_name} dut (
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.s_apb(s_apb)""")
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for port in slave_ports:
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f.write(f",\n .{port}({port})")
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f.write("""
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);
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// Dump waves
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initial begin
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$dumpfile("dump.vcd");
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$dumpvars(0, tb_{top_name});
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end
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endmodule
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""".format(top_name=top_name))
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return tb_path
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@skip_if_no_simulator
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def test_apb4_simple_register():
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"""Test APB4 decoder with a simple register."""
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rdl_source = """
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addrmap simple_test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} test_reg @ 0x0;
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};
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"""
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with tempfile.TemporaryDirectory() as tmpdir:
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tmpdir_path = Path(tmpdir)
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# Compile RDL and export SystemVerilog
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module_path, package_path = compile_rdl_and_export(
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rdl_source, "simple_test", str(tmpdir_path), APB4Cpuif
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)
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# Generate testbench wrapper
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tb_path = generate_testbench_wrapper(
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"simple_test", ["m_apb_test_reg"], tmpdir_path
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)
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# Get HDL source directory
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hdl_src_dir = Path(__file__).parent.parent.parent.parent / "hdl-src"
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# Run simulation using cocotb.runner
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from cocotb.runner import get_runner
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runner = get_runner("icarus")
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runner.build(
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verilog_sources=[
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str(hdl_src_dir / "apb4_intf.sv"),
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str(package_path),
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str(module_path),
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str(tb_path),
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],
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hdl_toplevel="tb_simple_test",
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always=True,
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build_dir=str(tmpdir_path / "sim_build"),
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)
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runner.test(
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hdl_toplevel="tb_simple_test",
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test_module="test_apb4_decoder",
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build_dir=str(tmpdir_path / "sim_build"),
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)
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@skip_if_no_simulator
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def test_apb4_multiple_registers():
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"""Test APB4 decoder with multiple registers."""
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rdl_source = """
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addrmap multi_reg {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} reg1 @ 0x0;
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reg {
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field {
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sw=r;
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hw=w;
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} status[15:0];
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} reg2 @ 0x4;
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reg {
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field {
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sw=rw;
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hw=r;
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} control[7:0];
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} reg3 @ 0x8;
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};
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"""
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with tempfile.TemporaryDirectory() as tmpdir:
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tmpdir_path = Path(tmpdir)
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# Compile RDL and export SystemVerilog
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module_path, package_path = compile_rdl_and_export(
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rdl_source, "multi_reg", str(tmpdir_path), APB4Cpuif
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)
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# Generate testbench wrapper
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tb_path = generate_testbench_wrapper(
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"multi_reg", ["m_apb_reg1", "m_apb_reg2", "m_apb_reg3"], tmpdir_path
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)
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# Get HDL source directory
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hdl_src_dir = Path(__file__).parent.parent.parent.parent / "hdl-src"
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# Run simulation
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from cocotb.runner import get_runner
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runner = get_runner("icarus")
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runner.build(
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verilog_sources=[
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str(hdl_src_dir / "apb4_intf.sv"),
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str(package_path),
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str(module_path),
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str(tb_path),
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],
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hdl_toplevel="tb_multi_reg",
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always=True,
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build_dir=str(tmpdir_path / "sim_build"),
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)
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runner.test(
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hdl_toplevel="tb_multi_reg",
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test_module="test_apb4_decoder",
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test_args=["--test-case=test_multiple_registers"],
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build_dir=str(tmpdir_path / "sim_build"),
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)
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