bslathi19/PeakRDL-BusDecoder
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remove apb4 wr_sel assrt

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Arnav Sacheti
2025-12-24 21:07:02 +00:00
parent ad364ab8d6
commit 549ebe6085
3 changed files with 2 additions and 4 deletions
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src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
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@@ -6,8 +6,6 @@
assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
end
assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("PSEL")}} && {{cpuif.signal("PWRITE")}} |-> ##1 ({{cpuif.signal("PREADY")}} || {{cpuif.signal("PSLVERR")}}))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif
{%- endif %}