added apb3 and axi4_lite
This commit is contained in:
Arnav Sacheti
@@ -54,14 +54,14 @@ interface axi4lite_intf #(
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modport slave (
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output AWREADY,
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input AWVALID,
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input AWADDR,
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// input AWVALID,
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// input AWADDR,
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input AWPROT,
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output WREADY,
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input WVALID,
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input WDATA,
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input WSTRB,
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// input WVALID,
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// input WDATA,
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// input WSTRB,
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input BREADY,
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output BVALID,
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@@ -73,8 +73,8 @@ interface axi4lite_intf #(
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input ARPROT,
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input RREADY,
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output RVALID,
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output RDATA,
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output RRESP
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// output RVALID,
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// output RDATA,
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// output RRESP
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);
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endinterface
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@@ -1,3 +1,5 @@
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from typing import overload
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from systemrdl.node import AddressableNode
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from ...utils import get_indexed_path
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@@ -10,11 +12,11 @@ class APB3Cpuif(BaseCpuif):
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def _port_declaration(self, child: AddressableNode) -> str:
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base = f"apb3_intf.master m_apb_{child.inst_name}"
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if not child.is_array:
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if child.array_dimensions is None:
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return base
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if child.current_idx is not None:
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return f"{base}_{'_'.join(map(str, child.current_idx))}"
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return f"{base} [N_{child.inst_name.upper()}S]"
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return f"{base}_{'_'.join(map(str, child.current_idx))} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
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return f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
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@property
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def port_declaration(self) -> str:
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@@ -23,36 +25,48 @@ class APB3Cpuif(BaseCpuif):
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return ",\n".join(slave_ports + master_ports)
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def signal(
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self,
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signal: str,
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node: AddressableNode | None = None,
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) -> str:
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if node is None:
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@overload
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def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
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@overload
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def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
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def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
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if node is None or indexer is None:
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# Node is none, so this is a slave signal
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return f"s_apb.{signal}"
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# Master signal
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return f"m_apb_{node.inst_name}.{signal}"
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return f"m_apb_{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
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def fanout(self, node: AddressableNode, idx: str | None = None) -> str:
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def fanout(self, node: AddressableNode) -> str:
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fanout: dict[str, str] = {}
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fanout[self.signal("PSEL", node, idx)] = (
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f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node)}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node)}"
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fanout[self.signal("PSEL", node, "gi")] = (
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f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
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)
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fanout[self.signal("PSEL", node, idx)] = self.signal("PSEL")
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fanout[self.signal("PWRITE", node, idx)] = (
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f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node)}"
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fanout[self.signal("PENABLE", node, "gi")] = self.signal("PENABLE")
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fanout[self.signal("PWRITE", node, "gi")] = (
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f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
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)
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fanout[self.signal("PADDR", node, idx)] = self.signal("PADDR")
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fanout[self.signal("PWDATA", node, idx)] = "cpuif_wr_data"
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fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR")
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fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
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return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
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def fanin(self, node: AddressableNode, idx: str | None = None) -> str:
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def fanin(self, node: AddressableNode | None = None) -> str:
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fanin: dict[str, str] = {}
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fanin["cpuif_rd_data"] = self.signal("PRDATA", node, idx)
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fanin["cpuif_rd_ack"] = self.signal("PREADY", node, idx)
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fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, idx)
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if node is None:
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fanin["cpuif_rd_ack"] = "'0"
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fanin["cpuif_rd_err"] = "'0"
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else:
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fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
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fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
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return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
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def readback(self, node: AddressableNode | None = None) -> str:
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fanin: dict[str, str] = {}
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if node is None:
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fanin["cpuif_rd_data"] = "'0"
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else:
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fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
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return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
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@@ -9,15 +9,18 @@
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`endif
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{% endif -%}
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assign cpuif_req = {{cpuif.signal("PSELx")}};
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assign cpuif_req = {{cpuif.signal("PSEL")}};
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assign cpuif_wr_en = {{cpuif.signal("PWRITE")}};
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assign cpuif_rd_en = !{{cpuif.signal("PWRITE")}};
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assign cpuif_wr_addr = {{cpuif.signal("PADDR")}};
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assign cpuif_rd_addr = {{cpuif.signal("PADDR")}};
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assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
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assign {{cpuif.signal("PRDATA")}} = cpuif_rd_data;
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assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack;
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assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err;
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assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
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//--------------------------------------------------------------------------
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// Fanout CPU Bus interface signals
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@@ -1,67 +0,0 @@
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from ..base_cpuif import CpuifBase
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class AXI4Lite_Cpuif(CpuifBase):
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template_path = "axi4lite_tmpl.sv"
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is_interface = True
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@property
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def port_declaration(self) -> str:
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return "axi4lite_intf.slave s_axil"
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def signal(self, name: str) -> str:
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return "s_axil." + name.upper()
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@property
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def busdecoder_latency(self) -> int:
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return max(self.exp.ds.min_read_latency, self.exp.ds.min_write_latency)
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@property
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def max_outstanding(self) -> int:
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"""
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Best pipelined performance is when the max outstanding transactions
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is the design's latency + 2.
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Anything beyond that does not have any effect, aside from adding unnecessary
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logic and additional buffer-bloat latency.
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"""
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return self.busdecoder_latency + 2
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@property
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def resp_buffer_size(self) -> int:
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"""
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Response buffer size must be greater or equal to max outstanding
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transactions to prevent response overrun.
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"""
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return self.max_outstanding
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class AXI4Lite_Cpuif_flattened(AXI4Lite_Cpuif):
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is_interface = False
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@property
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def port_declaration(self) -> str:
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lines = [
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"output logic " + self.signal("awready"),
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"input wire " + self.signal("awvalid"),
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f"input wire [{self.addr_width - 1}:0] " + self.signal("awaddr"),
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"input wire [2:0] " + self.signal("awprot"),
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"output logic " + self.signal("wready"),
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"input wire " + self.signal("wvalid"),
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f"input wire [{self.data_width - 1}:0] " + self.signal("wdata"),
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f"input wire [{self.data_width_bytes - 1}:0]" + self.signal("wstrb"),
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"input wire " + self.signal("bready"),
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"output logic " + self.signal("bvalid"),
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"output logic [1:0] " + self.signal("bresp"),
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"output logic " + self.signal("arready"),
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"input wire " + self.signal("arvalid"),
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f"input wire [{self.addr_width - 1}:0] " + self.signal("araddr"),
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"input wire [2:0] " + self.signal("arprot"),
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"input wire " + self.signal("rready"),
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"output logic " + self.signal("rvalid"),
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f"output logic [{self.data_width - 1}:0] " + self.signal("rdata"),
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"output logic [1:0] " + self.signal("rresp"),
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]
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return ",\n".join(lines)
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def signal(self, name: str) -> str:
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return "s_axil_" + name
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89
src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py
Normal file
89
src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py
Normal file
@@ -0,0 +1,89 @@
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from typing import overload
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from systemrdl.node import AddressableNode
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from ...utils import get_indexed_path
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from ..base_cpuif import BaseCpuif
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class AXI4LiteCpuif(BaseCpuif):
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template_path = "axi4lite_tmpl.sv"
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is_interface = True
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def _port_declaration(self, child: AddressableNode) -> str:
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base = f"axi4lite_intf.master m_axil_{child.inst_name}"
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if child.array_dimensions is None:
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return base
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if child.current_idx is not None:
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return f"{base}_{'_'.join(map(str, child.current_idx))} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
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return f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
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@property
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def port_declaration(self) -> str:
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"""Returns the port declaration for the AXI4-Lite interface."""
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slave_ports: list[str] = ["axi4lite_intf.slave s_axil"]
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master_ports: list[str] = list(map(self._port_declaration, self.addressable_children))
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return ",\n".join(slave_ports + master_ports)
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@overload
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def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
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@overload
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def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
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def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
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if node is None or indexer is None:
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# Node is none, so this is a slave signal
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return f"s_axil.{signal}"
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# Master signal
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return f"m_axil_{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
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def fanout(self, node: AddressableNode) -> str:
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fanout: dict[str, str] = {}
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wr_sel = f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
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rd_sel = f"cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
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# Write address channel
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fanout[self.signal("AWVALID", node, "gi")] = wr_sel
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fanout[self.signal("AWADDR", node, "gi")] = self.signal("AWADDR")
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fanout[self.signal("AWPROT", node, "gi")] = self.signal("AWPROT")
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# Write data channel
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fanout[self.signal("WVALID", node, "gi")] = wr_sel
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fanout[self.signal("WDATA", node, "gi")] = "cpuif_wr_data"
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fanout[self.signal("WSTRB", node, "gi")] = "cpuif_wr_byte_en"
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# Write response channel (master -> slave)
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fanout[self.signal("BREADY", node, "gi")] = self.signal("BREADY")
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# Read address channel
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fanout[self.signal("ARVALID", node, "gi")] = rd_sel
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fanout[self.signal("ARADDR", node, "gi")] = self.signal("ARADDR")
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fanout[self.signal("ARPROT", node, "gi")] = self.signal("ARPROT")
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# Read data channel (master -> slave)
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fanout[self.signal("RREADY", node, "gi")] = self.signal("RREADY")
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return "\n".join(f"assign {lhs} = {rhs};" for lhs, rhs in fanout.items())
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def fanin(self, node: AddressableNode | None = None) -> str:
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fanin: dict[str, str] = {}
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if node is None:
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fanin["cpuif_rd_ack"] = "'0"
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fanin["cpuif_rd_err"] = "'0"
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else:
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# Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
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fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
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fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
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return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
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def readback(self, node: AddressableNode | None = None) -> str:
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fanin: dict[str, str] = {}
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if node is None:
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fanin["cpuif_rd_data"] = "'0"
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else:
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fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
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return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
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@@ -1,254 +1,60 @@
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{%- if cpuif.is_interface -%}
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`ifndef SYNTHESIS
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initial begin
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assert_bad_addr_width: assert($bits({{cpuif.signal("araddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
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else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("araddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
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assert_bad_data_width: assert($bits({{cpuif.signal("wdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
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else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("wdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
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end
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`endif
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// Width checks (AXI4-Lite)
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assert_bad_awaddr_width: assert($bits({{cpuif.signal("AWADDR")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
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else $error("AWADDR width %0d < MIN_ADDR_WIDTH %0d",
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$bits({{cpuif.signal("AWADDR")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
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assert_bad_araddr_width: assert($bits({{cpuif.signal("ARADDR")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
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else $error("ARADDR width %0d < MIN_ADDR_WIDTH %0d",
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$bits({{cpuif.signal("ARADDR")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
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assert_bad_data_width: assert($bits({{cpuif.signal("WDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
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else $error("WDATA width %0d != DATA_WIDTH %0d",
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$bits({{cpuif.signal("WDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
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end
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// Simple handshake sanity (one-cycle implication; relax/adjust as needed)
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assert_rd_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
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{{cpuif.signal("RVALID")}} |-> (^{{cpuif.signal("RRESP")}} !== 1'bx))
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else $error("RRESP must be a legal AXI response when RVALID is high");
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assert_wr_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
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{{cpuif.signal("BVALID")}} |-> (^{{cpuif.signal("BRESP")}} !== 1'bx))
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else $error("BRESP must be a legal AXI response when BVALID is high");
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`endif
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{% endif -%}
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// Max Outstanding Transactions: {{cpuif.max_outstanding}}
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logic [{{clog2(cpuif.max_outstanding+1)-1}}:0] axil_n_in_flight;
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logic axil_prev_was_rd;
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logic axil_arvalid;
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logic [{{cpuif.addr_width-1}}:0] axil_araddr;
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logic axil_ar_accept;
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logic axil_awvalid;
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logic [{{cpuif.addr_width-1}}:0] axil_awaddr;
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logic axil_wvalid;
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logic [{{cpuif.data_width-1}}:0] axil_wdata;
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logic [{{cpuif.data_width_bytes-1}}:0] axil_wstrb;
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logic axil_aw_accept;
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logic axil_resp_acked;
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// Transaction request acceptance
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always_ff {{get_always_ff_event(cpuif.reset)}} begin
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if({{get_resetsignal(cpuif.reset)}}) begin
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axil_prev_was_rd <= '0;
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axil_arvalid <= '0;
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axil_araddr <= '0;
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axil_awvalid <= '0;
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axil_awaddr <= '0;
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axil_wvalid <= '0;
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axil_wdata <= '0;
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axil_wstrb <= '0;
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axil_n_in_flight <= '0;
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end else begin
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// AR* acceptance register
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if(axil_ar_accept) begin
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axil_prev_was_rd <= '1;
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axil_arvalid <= '0;
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end
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if({{cpuif.signal("arvalid")}} && {{cpuif.signal("arready")}}) begin
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axil_arvalid <= '1;
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axil_araddr <= {{cpuif.signal("araddr")}};
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end
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assign cpuif_req = {{cpuif.signal("AWVALID")}} | {{cpuif.signal("ARVALID")}};
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assign cpuif_wr_en = {{cpuif.signal("AWVALID")}} & {{cpuif.signal("WVALID")}};
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assign cpuif_rd_en = {{cpuif.signal("ARVALID")}};
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// AW* & W* acceptance registers
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if(axil_aw_accept) begin
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axil_prev_was_rd <= '0;
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axil_awvalid <= '0;
|
||||
axil_wvalid <= '0;
|
||||
end
|
||||
if({{cpuif.signal("awvalid")}} && {{cpuif.signal("awready")}}) begin
|
||||
axil_awvalid <= '1;
|
||||
axil_awaddr <= {{cpuif.signal("awaddr")}};
|
||||
end
|
||||
if({{cpuif.signal("wvalid")}} && {{cpuif.signal("wready")}}) begin
|
||||
axil_wvalid <= '1;
|
||||
axil_wdata <= {{cpuif.signal("wdata")}};
|
||||
axil_wstrb <= {{cpuif.signal("wstrb")}};
|
||||
end
|
||||
assign cpuif_wr_addr = {{cpuif.signal("AWADDR")}};
|
||||
assign cpuif_rd_addr = {{cpuif.signal("ARADDR")}};
|
||||
|
||||
// Keep track of in-flight transactions
|
||||
if((axil_ar_accept || axil_aw_accept) && !axil_resp_acked) begin
|
||||
axil_n_in_flight <= axil_n_in_flight + 1'b1;
|
||||
end else if(!(axil_ar_accept || axil_aw_accept) && axil_resp_acked) begin
|
||||
axil_n_in_flight <= axil_n_in_flight - 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
assign cpuif_wr_data = {{cpuif.signal("WDATA")}};
|
||||
assign cpuif_wr_byte_en = {{cpuif.signal("WSTRB")}};
|
||||
|
||||
always_comb begin
|
||||
{{cpuif.signal("arready")}} = (!axil_arvalid || axil_ar_accept);
|
||||
{{cpuif.signal("awready")}} = (!axil_awvalid || axil_aw_accept);
|
||||
{{cpuif.signal("wready")}} = (!axil_wvalid || axil_aw_accept);
|
||||
end
|
||||
//
|
||||
// Return paths back to AXI master from generic cpuif_*
|
||||
// Read: ack=RVALID, err=RRESP[1] (SLVERR/DECERR), data=RDATA
|
||||
//
|
||||
assign {{cpuif.signal("RDATA")}} = cpuif_rd_data;
|
||||
assign {{cpuif.signal("RVALID")}} = cpuif_rd_ack;
|
||||
assign {{cpuif.signal("RRESP")}} = (cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err) ? 2'b10 : 2'b00;
|
||||
|
||||
// Request dispatch
|
||||
always_comb begin
|
||||
cpuif_wr_data = axil_wdata;
|
||||
for(int i=0; i<{{cpuif.data_width_bytes}}; i++) begin
|
||||
cpuif_wr_biten[i*8 +: 8] = {8{axil_wstrb[i]}};
|
||||
end
|
||||
cpuif_req = '0;
|
||||
cpuif_req_is_wr = '0;
|
||||
cpuif_addr = '0;
|
||||
axil_ar_accept = '0;
|
||||
axil_aw_accept = '0;
|
||||
// Write: ack=BVALID, err=BRESP[1]
|
||||
assign {{cpuif.signal("BVALID")}} = cpuif_wr_ack;
|
||||
assign {{cpuif.signal("BRESP")}} = (cpuif_wr_err | cpuif_wr_sel.cpuif_err | cpuif_rd_sel.cpuif_err) ? 2'b10 : 2'b00;
|
||||
|
||||
if(axil_n_in_flight < {{clog2(cpuif.max_outstanding+1)}}'d{{cpuif.max_outstanding}}) begin
|
||||
// Can safely issue more transactions without overwhelming response buffer
|
||||
if(axil_arvalid && !axil_prev_was_rd) begin
|
||||
cpuif_req = '1;
|
||||
cpuif_req_is_wr = '0;
|
||||
{%- if cpuif.data_width_bytes == 1 %}
|
||||
cpuif_addr = axil_araddr;
|
||||
{%- else %}
|
||||
cpuif_addr = {axil_araddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
|
||||
{%- endif %}
|
||||
if(!cpuif_req_stall_rd) axil_ar_accept = '1;
|
||||
end else if(axil_awvalid && axil_wvalid) begin
|
||||
cpuif_req = '1;
|
||||
cpuif_req_is_wr = '1;
|
||||
{%- if cpuif.data_width_bytes == 1 %}
|
||||
cpuif_addr = axil_awaddr;
|
||||
{%- else %}
|
||||
cpuif_addr = {axil_awaddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
|
||||
{%- endif %}
|
||||
if(!cpuif_req_stall_wr) axil_aw_accept = '1;
|
||||
end else if(axil_arvalid) begin
|
||||
cpuif_req = '1;
|
||||
cpuif_req_is_wr = '0;
|
||||
{%- if cpuif.data_width_bytes == 1 %}
|
||||
cpuif_addr = axil_araddr;
|
||||
{%- else %}
|
||||
cpuif_addr = {axil_araddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
|
||||
{%- endif %}
|
||||
if(!cpuif_req_stall_rd) axil_ar_accept = '1;
|
||||
end
|
||||
end
|
||||
end
|
||||
//--------------------------------------------------------------------------
|
||||
// Fanout CPU Bus interface signals
|
||||
//--------------------------------------------------------------------------
|
||||
{{fanout|walk(cpuif=cpuif)}}
|
||||
|
||||
|
||||
// AXI4-Lite Response Logic
|
||||
{%- if cpuif.resp_buffer_size == 1 %}
|
||||
always_ff {{get_always_ff_event(cpuif.reset)}} begin
|
||||
if({{get_resetsignal(cpuif.reset)}}) begin
|
||||
{{cpuif.signal("rvalid")}} <= '0;
|
||||
{{cpuif.signal("rresp")}} <= '0;
|
||||
{{cpuif.signal("rdata")}} <= '0;
|
||||
{{cpuif.signal("bvalid")}} <= '0;
|
||||
{{cpuif.signal("bresp")}} <= '0;
|
||||
end else begin
|
||||
if({{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) begin
|
||||
{{cpuif.signal("rvalid")}} <= '0;
|
||||
end
|
||||
|
||||
if({{cpuif.signal("bvalid")}} && {{cpuif.signal("bready")}}) begin
|
||||
{{cpuif.signal("bvalid")}} <= '0;
|
||||
end
|
||||
|
||||
if(cpuif_rd_ack) begin
|
||||
{{cpuif.signal("rvalid")}} <= '1;
|
||||
{{cpuif.signal("rdata")}} <= cpuif_rd_data;
|
||||
if(cpuif_rd_err) {{cpuif.signal("rresp")}} <= 2'b10; // SLVERR
|
||||
else {{cpuif.signal("rresp")}} <= 2'b00; // OKAY
|
||||
end
|
||||
|
||||
if(cpuif_wr_ack) begin
|
||||
{{cpuif.signal("bvalid")}} <= '1;
|
||||
if(cpuif_wr_err) {{cpuif.signal("bresp")}} <= 2'b10; // SLVERR
|
||||
else {{cpuif.signal("bresp")}} <= 2'b00; // OKAY
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
axil_resp_acked = '0;
|
||||
if({{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) axil_resp_acked = '1;
|
||||
if({{cpuif.signal("bvalid")}} && {{cpuif.signal("bready")}}) axil_resp_acked = '1;
|
||||
end
|
||||
|
||||
{%- else %}
|
||||
struct {
|
||||
logic is_wr;
|
||||
logic err;
|
||||
logic [{{cpuif.data_width-1}}:0] rdata;
|
||||
} axil_resp_buffer[{{roundup_pow2(cpuif.resp_buffer_size)}}];
|
||||
{%- if not is_pow2(cpuif.resp_buffer_size) %}
|
||||
// axil_resp_buffer is intentionally padded to the next power of two despite
|
||||
// only requiring {{cpuif.resp_buffer_size}} entries.
|
||||
// This is to avoid quirks in some tools that cannot handle indexing into a non-power-of-2 array.
|
||||
// Unused entries are expected to be optimized away
|
||||
{% endif %}
|
||||
|
||||
logic [{{clog2(cpuif.resp_buffer_size)}}:0] axil_resp_wptr;
|
||||
logic [{{clog2(cpuif.resp_buffer_size)}}:0] axil_resp_rptr;
|
||||
|
||||
always_ff {{get_always_ff_event(cpuif.reset)}} begin
|
||||
if({{get_resetsignal(cpuif.reset)}}) begin
|
||||
for(int i=0; i<{{cpuif.resp_buffer_size}}; i++) begin
|
||||
axil_resp_buffer[i].is_wr <= '0;
|
||||
axil_resp_buffer[i].err <= '0;
|
||||
axil_resp_buffer[i].rdata <= '0;
|
||||
end
|
||||
axil_resp_wptr <= '0;
|
||||
axil_resp_rptr <= '0;
|
||||
end else begin
|
||||
// Store responses in buffer until AXI response channel accepts them
|
||||
if(cpuif_rd_ack || cpuif_wr_ack) begin
|
||||
if(cpuif_rd_ack) begin
|
||||
axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].is_wr <= '0;
|
||||
axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].err <= cpuif_rd_err;
|
||||
axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].rdata <= cpuif_rd_data;
|
||||
|
||||
end else if(cpuif_wr_ack) begin
|
||||
axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].is_wr <= '1;
|
||||
axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].err <= cpuif_wr_err;
|
||||
end
|
||||
{%- if is_pow2(cpuif.resp_buffer_size) %}
|
||||
axil_resp_wptr <= axil_resp_wptr + 1'b1;
|
||||
{%- else %}
|
||||
if(axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] == {{cpuif.resp_buffer_size-1}}) begin
|
||||
axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= '0;
|
||||
axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)}}] <= ~axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)}}];
|
||||
end else begin
|
||||
axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] + 1'b1;
|
||||
end
|
||||
{%- endif %}
|
||||
end
|
||||
|
||||
// Advance read pointer when acknowledged
|
||||
if(axil_resp_acked) begin
|
||||
{%- if is_pow2(cpuif.resp_buffer_size) %}
|
||||
axil_resp_rptr <= axil_resp_rptr + 1'b1;
|
||||
{%- else %}
|
||||
if(axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] == {{cpuif.resp_buffer_size-1}}) begin
|
||||
axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= '0;
|
||||
axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)}}] <= ~axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)}}];
|
||||
end else begin
|
||||
axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] + 1'b1;
|
||||
end
|
||||
{%- endif %}
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
axil_resp_acked = '0;
|
||||
{{cpuif.signal("bvalid")}} = '0;
|
||||
{{cpuif.signal("rvalid")}} = '0;
|
||||
if(axil_resp_rptr != axil_resp_wptr) begin
|
||||
if(axil_resp_buffer[axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].is_wr) begin
|
||||
{{cpuif.signal("bvalid")}} = '1;
|
||||
if({{cpuif.signal("bready")}}) axil_resp_acked = '1;
|
||||
end else begin
|
||||
{{cpuif.signal("rvalid")}} = '1;
|
||||
if({{cpuif.signal("rready")}}) axil_resp_acked = '1;
|
||||
end
|
||||
end
|
||||
|
||||
{{cpuif.signal("rdata")}} = axil_resp_buffer[axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].rdata;
|
||||
if(axil_resp_buffer[axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].err) begin
|
||||
{{cpuif.signal("bresp")}} = 2'b10;
|
||||
{{cpuif.signal("rresp")}} = 2'b10;
|
||||
end else begin
|
||||
{{cpuif.signal("bresp")}} = 2'b00;
|
||||
{{cpuif.signal("rresp")}} = 2'b00;
|
||||
end
|
||||
end
|
||||
{%- endif %}
|
||||
//--------------------------------------------------------------------------
|
||||
// Fanin CPU Bus interface signals
|
||||
//--------------------------------------------------------------------------
|
||||
{{fanin|walk(cpuif=cpuif)}}
|
||||
Reference in New Issue
Block a user