bslathi19/PeakRDL-BusDecoder
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added apb3 and axi4_lite

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This commit is contained in:
Arnav Sacheti
2025-10-21 22:29:10 -07:00
parent 395f584f52
commit 740d4a84ac
6 changed files with 185 additions and 340 deletions
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58
src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py
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@@ -1,3 +1,5 @@
from typing import overload
from systemrdl.node import AddressableNode
from ...utils import get_indexed_path
@@ -10,11 +12,11 @@ class APB3Cpuif(BaseCpuif):
def _port_declaration(self, child: AddressableNode) -> str:
base = f"apb3_intf.master m_apb_{child.inst_name}"
if not child.is_array:
if child.array_dimensions is None:
return base
if child.current_idx is not None:
return f"{base}_{'_'.join(map(str, child.current_idx))}"
return f"{base} [N_{child.inst_name.upper()}S]"
return f"{base}_{'_'.join(map(str, child.current_idx))} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
return f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
@property
def port_declaration(self) -> str:
@@ -23,36 +25,48 @@ class APB3Cpuif(BaseCpuif):
return ",\n".join(slave_ports + master_ports)
def signal(
self,
signal: str,
node: AddressableNode | None = None,
) -> str:
if node is None:
@overload
def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
@overload
def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
if node is None or indexer is None:
# Node is none, so this is a slave signal
return f"s_apb.{signal}"
# Master signal
return f"m_apb_{node.inst_name}.{signal}"
return f"m_apb_{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
def fanout(self, node: AddressableNode, idx: str | None = None) -> str:
def fanout(self, node: AddressableNode) -> str:
fanout: dict[str, str] = {}
fanout[self.signal("PSEL", node, idx)] = (
f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node)}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node)}"
fanout[self.signal("PSEL", node, "gi")] = (
f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
)
fanout[self.signal("PSEL", node, idx)] = self.signal("PSEL")
fanout[self.signal("PWRITE", node, idx)] = (
f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node)}"
fanout[self.signal("PENABLE", node, "gi")] = self.signal("PENABLE")
fanout[self.signal("PWRITE", node, "gi")] = (
f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
)
fanout[self.signal("PADDR", node, idx)] = self.signal("PADDR")
fanout[self.signal("PWDATA", node, idx)] = "cpuif_wr_data"
fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR")
fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
def fanin(self, node: AddressableNode, idx: str | None = None) -> str:
def fanin(self, node: AddressableNode | None = None) -> str:
fanin: dict[str, str] = {}
fanin["cpuif_rd_data"] = self.signal("PRDATA", node, idx)
fanin["cpuif_rd_ack"] = self.signal("PREADY", node, idx)
fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, idx)
if node is None:
fanin["cpuif_rd_ack"] = "'0"
fanin["cpuif_rd_err"] = "'0"
else:
fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
def readback(self, node: AddressableNode | None = None) -> str:
fanin: dict[str, str] = {}
if node is None:
fanin["cpuif_rd_data"] = "'0"
else:
fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))