Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/lib/cpuifs/avalon/__init__.py

@@ -0,0 +1,18 @@
+from ..base import CpuifTestMode
+
+from peakrdl_regblock.cpuif.avalon import Avalon_Cpuif, Avalon_Cpuif_flattened
+
+class Avalon(CpuifTestMode):
+    cpuif_cls = Avalon_Cpuif
+    rtl_files = [
+        "../../../../hdl-src/avalon_mm_intf.sv",
+    ]
+    tb_files = [
+        "../../../../hdl-src/avalon_mm_intf.sv",
+        "avalon_mm_intf_driver.sv",
+    ]
+    tb_template = "tb_inst.sv"
+
+class FlatAvalon(Avalon):
+    cpuif_cls = Avalon_Cpuif_flattened
+    rtl_files = []

tests/lib/cpuifs/avalon/avalon_mm_intf_driver.sv

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+interface avalon_mm_intf_driver #(
+        parameter DATA_WIDTH = 32,
+        parameter ADDR_WIDTH = 32
+    )(
+        input wire clk,
+        input wire rst,
+        avalon_mm_intf.host avalon
+    );
+    timeunit 1ps;
+    timeprecision 1ps;
+
+    localparam ADDR_PAD = $clog2(DATA_WIDTH/8);
+    localparam WORD_ADDR_WIDTH = ADDR_WIDTH - ADDR_PAD;
+
+    logic av_read;
+    logic av_write;
+    logic av_waitrequest;
+    logic [WORD_ADDR_WIDTH-1:0] av_address;
+    logic [DATA_WIDTH-1:0] av_writedata;
+    logic [DATA_WIDTH/8-1:0] av_byteenable;
+    logic av_readdatavalid;
+    logic av_writeresponsevalid;
+    logic [DATA_WIDTH-1:0] av_readdata;
+    logic [1:0] av_response;
+
+    assign avalon.read = av_read;
+    assign avalon.write = av_write;
+    assign av_waitrequest = avalon.waitrequest;
+    assign avalon.address = av_address;
+    assign avalon.writedata = av_writedata;
+    assign avalon.byteenable = av_byteenable;
+    assign av_readdatavalid = avalon.readdatavalid;
+    assign av_writeresponsevalid = avalon.writeresponsevalid;
+    assign av_readdata = avalon.readdata;
+    assign av_response = avalon.response;
+
+    default clocking cb @(posedge clk);
+        default input #1step output #1;
+        output av_read;
+        output av_write;
+        input av_waitrequest;
+        output av_address;
+        output av_writedata;
+        output av_byteenable;
+        input av_readdatavalid;
+        input av_writeresponsevalid;
+        input av_readdata;
+        input av_response;
+    endclocking
+
+    task automatic reset();
+        cb.av_read <= '0;
+        cb.av_write <= '0;
+        cb.av_address <= '0;
+        cb.av_writedata <= '0;
+        cb.av_byteenable <= '0;
+    endtask
+
+    semaphore req_mutex = new(1);
+    semaphore resp_mutex = new(1);
+
+    task automatic write(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] data, logic [DATA_WIDTH/8-1:0] strb = '1);
+        fork
+            begin
+                req_mutex.get();
+                ##0;
+                // Initiate transfer
+                cb.av_write <= '1;
+                cb.av_address <= (addr >> ADDR_PAD);
+                cb.av_writedata <= data;
+                cb.av_byteenable <= strb;
+                @(cb);
+
+                // Wait for transfer to be accepted
+                while(cb.av_waitrequest == 1'b1) @(cb);
+                reset();
+                req_mutex.put();
+            end
+
+            begin
+                resp_mutex.get();
+                @cb;
+                // Wait for response
+                while(cb.av_writeresponsevalid !== 1'b1) @(cb);
+                assert(!$isunknown(cb.av_response)) else $error("Read from 0x%0x returned X's on av_response", addr);
+                resp_mutex.put();
+            end
+        join
+    endtask
+
+    task automatic read(logic [ADDR_WIDTH-1:0] addr, output logic [DATA_WIDTH-1:0] data);
+        fork
+            begin
+                req_mutex.get();
+                ##0;
+                // Initiate transfer
+                cb.av_read <= '1;
+                cb.av_address <= (addr >> ADDR_PAD);
+                @(cb);
+
+                // Wait for transfer to be accepted
+                while(cb.av_waitrequest == 1'b1) @(cb);
+                reset();
+                req_mutex.put();
+            end
+
+            begin
+                resp_mutex.get();
+                @cb;
+                // Wait for response
+                while(cb.av_readdatavalid !== 1'b1) @(cb);
+                assert(!$isunknown(cb.av_readdata)) else $error("Read from 0x%0x returned X's on av_response", av_readdata);
+                assert(!$isunknown(cb.av_response)) else $error("Read from 0x%0x returned X's on av_response", addr);
+                data = cb.av_readdata;
+                resp_mutex.put();
+            end
+        join
+    endtask
+
+    task automatic assert_read(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] expected_data, logic [DATA_WIDTH-1:0] mask = '1);
+        logic [DATA_WIDTH-1:0] data;
+        read(addr, data);
+        data &= mask;
+        assert(data == expected_data) else $error("Read from 0x%x returned 0x%x. Expected 0x%x", addr, data, expected_data);
+    endtask
+
+    initial begin
+        reset();
+    end
+
+    initial forever begin
+        @cb;
+        if(!rst) assert(!$isunknown(cb.av_waitrequest)) else $error("Saw X on av_waitrequest!");
+        if(!rst) assert(!$isunknown(cb.av_readdatavalid)) else $error("Saw X on av_readdatavalid!");
+        if(!rst) assert(!$isunknown(cb.av_writeresponsevalid)) else $error("Saw X on av_writeresponsevalid!");
+    end
+
+endinterface

tests/lib/cpuifs/avalon/tb_inst.sv

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+{% sv_line_anchor %}
+avalon_mm_intf #(
+    .DATA_WIDTH({{exporter.cpuif.data_width}}),
+    .ADDR_WIDTH({{exporter.cpuif.word_addr_width}})
+) avalon();
+avalon_mm_intf_driver #(
+    .DATA_WIDTH({{exporter.cpuif.data_width}}),
+    .ADDR_WIDTH({{exporter.cpuif.addr_width}})
+) cpuif (
+    .clk(clk),
+    .rst(rst),
+    .avalon(avalon)
+);
+{% if type(cpuif).__name__.startswith("Flat") %}
+{% sv_line_anchor %}
+wire avalon_read;
+wire avalon_write;
+wire avalon_waitrequest;
+wire [{{exporter.cpuif.word_addr_width - 1}}:0] avalon_address;
+wire [{{exporter.cpuif.data_width - 1}}:0] avalon_writedata;
+wire [{{exporter.cpuif.data_width_bytes - 1}}:0] avalon_byteenable;
+wire avalon_readdatavalid;
+wire avalon_writeresponsevalid;
+wire [{{exporter.cpuif.data_width - 1}}:0] avalon_readdata;
+wire [1:0] avalon_response;
+assign avalon_read = avalon.read;
+assign avalon_write = avalon.write;
+assign avalon.waitrequest = avalon_waitrequest;
+assign avalon_address = avalon.address;
+assign avalon_writedata = avalon.writedata;
+assign avalon_byteenable = avalon.byteenable;
+assign avalon.readdatavalid = avalon_readdatavalid;
+assign avalon.writeresponsevalid = avalon_writeresponsevalid;
+assign avalon.readdata = avalon_readdata;
+assign avalon.response = avalon_response;
+{% endif %}