9bf5cd1e6833af41b332b5a4e48337ab34d9133d
PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
For the command line tool, see the PeakRDL project.
Documentation
See the PeakRDL-regblock Documentation for more details
Description
Languages
Python
93.6%
SystemVerilog
6.2%
Dockerfile
0.2%