Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/lib/cpuifs/passthrough/__init__.py

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+from ..base import CpuifTestMode
+
+from peakrdl_regblock.cpuif.passthrough import PassthroughCpuif
+
+class Passthrough(CpuifTestMode):
+    cpuif_cls = PassthroughCpuif
+    rtl_files = []
+    tb_files = [
+        "passthrough_driver.sv",
+    ]
+    tb_template = "tb_inst.sv"

tests/lib/cpuifs/passthrough/passthrough_driver.sv

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+interface passthrough_driver #(
+        parameter DATA_WIDTH = 32,
+        parameter ADDR_WIDTH = 32
+    )(
+        input wire clk,
+        input wire rst,
+
+        output logic m_cpuif_req,
+        output logic m_cpuif_req_is_wr,
+        output logic [ADDR_WIDTH-1:0] m_cpuif_addr,
+        output logic [DATA_WIDTH-1:0] m_cpuif_wr_data,
+        output logic [DATA_WIDTH-1:0] m_cpuif_wr_biten,
+        input wire m_cpuif_req_stall_wr,
+        input wire m_cpuif_req_stall_rd,
+        input wire m_cpuif_rd_ack,
+        input wire m_cpuif_rd_err,
+        input wire [DATA_WIDTH-1:0] m_cpuif_rd_data,
+        input wire m_cpuif_wr_ack,
+        input wire m_cpuif_wr_err
+    );
+
+    timeunit 1ps;
+    timeprecision 1ps;
+
+    default clocking cb @(posedge clk);
+        default input #1step output #1;
+        output m_cpuif_req;
+        output m_cpuif_req_is_wr;
+        output m_cpuif_addr;
+        output m_cpuif_wr_data;
+        output m_cpuif_wr_biten;
+        input m_cpuif_req_stall_wr;
+        input m_cpuif_req_stall_rd;
+        input m_cpuif_rd_ack;
+        input m_cpuif_rd_err;
+        input m_cpuif_rd_data;
+        input m_cpuif_wr_ack;
+        input m_cpuif_wr_err;
+    endclocking
+
+    task automatic reset();
+        cb.m_cpuif_req <= '0;
+        cb.m_cpuif_req_is_wr <= '0;
+        cb.m_cpuif_addr <= '0;
+        cb.m_cpuif_wr_data <= '0;
+        cb.m_cpuif_wr_biten <= '0;
+    endtask
+
+    semaphore txn_req_mutex = new(1);
+    semaphore txn_resp_mutex = new(1);
+
+    task automatic write(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] data, logic [DATA_WIDTH-1:0] biten = '1);
+        fork
+            begin
+                // Initiate transfer
+                txn_req_mutex.get();
+                ##0;
+                cb.m_cpuif_req <= '1;
+                cb.m_cpuif_req_is_wr <= '1;
+                cb.m_cpuif_addr <= addr;
+                cb.m_cpuif_wr_data <= data;
+                cb.m_cpuif_wr_biten <= biten;
+                @(cb);
+                while(cb.m_cpuif_req_stall_wr !== 1'b0) @(cb);
+                reset();
+                txn_req_mutex.put();
+            end
+
+            begin
+                // Wait for response
+                txn_resp_mutex.get();
+                @cb;
+                while(cb.m_cpuif_wr_ack !== 1'b1) @(cb);
+                txn_resp_mutex.put();
+            end
+        join
+    endtask
+
+    task automatic read(logic [ADDR_WIDTH-1:0] addr, output logic [DATA_WIDTH-1:0] data);
+        fork
+            begin
+                // Initiate transfer
+                txn_req_mutex.get();
+                ##0;
+                cb.m_cpuif_req <= '1;
+                cb.m_cpuif_req_is_wr <= '0;
+                cb.m_cpuif_addr <= addr;
+                @(cb);
+                while(cb.m_cpuif_req_stall_rd !== 1'b0) @(cb);
+                reset();
+                txn_req_mutex.put();
+            end
+
+            begin
+                // Wait for response
+                txn_resp_mutex.get();
+                @cb;
+                while(cb.m_cpuif_rd_ack !== 1'b1) @(cb);
+                assert(!$isunknown(cb.m_cpuif_rd_data)) else $error("Read from 0x%0x returned X's on m_cpuif_rd_data", addr);
+                data = cb.m_cpuif_rd_data;
+                txn_resp_mutex.put();
+            end
+        join
+    endtask
+
+    task automatic assert_read(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] expected_data, logic [DATA_WIDTH-1:0] mask = '1);
+        logic [DATA_WIDTH-1:0] data;
+        read(addr, data);
+        data &= mask;
+        assert(data == expected_data) else $error("Read from 0x%x returned 0x%x. Expected 0x%x", addr, data, expected_data);
+    endtask
+
+    initial begin
+        reset();
+    end
+
+    initial forever begin
+        @cb;
+        if(!rst) assert(!$isunknown(cb.m_cpuif_rd_ack)) else $error("Saw X on m_cpuif_rd_ack!");
+        if(!rst) assert(!$isunknown(cb.m_cpuif_wr_ack)) else $error("Saw X on m_cpuif_wr_ack!");
+    end
+
+endinterface

tests/lib/cpuifs/passthrough/tb_inst.sv

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+{% sv_line_anchor %}
+wire s_cpuif_req;
+wire s_cpuif_req_is_wr;
+wire [{{exporter.cpuif.addr_width-1}}:0] s_cpuif_addr;
+wire [{{exporter.cpuif.data_width-1}}:0] s_cpuif_wr_data;
+wire [{{exporter.cpuif.data_width-1}}:0] s_cpuif_wr_biten;
+wire s_cpuif_req_stall_wr;
+wire s_cpuif_req_stall_rd;
+wire s_cpuif_rd_ack;
+wire s_cpuif_rd_err;
+wire [{{exporter.cpuif.data_width-1}}:0] s_cpuif_rd_data;
+wire s_cpuif_wr_ack;
+wire s_cpuif_wr_err;
+passthrough_driver #(
+    .DATA_WIDTH({{exporter.cpuif.data_width}}),
+    .ADDR_WIDTH({{exporter.cpuif.addr_width}})
+) cpuif (
+    .clk(clk),
+    .rst(rst),
+    .m_cpuif_req(s_cpuif_req),
+    .m_cpuif_req_is_wr(s_cpuif_req_is_wr),
+    .m_cpuif_addr(s_cpuif_addr),
+    .m_cpuif_wr_data(s_cpuif_wr_data),
+    .m_cpuif_wr_biten(s_cpuif_wr_biten),
+    .m_cpuif_req_stall_wr(s_cpuif_req_stall_wr),
+    .m_cpuif_req_stall_rd(s_cpuif_req_stall_rd),
+    .m_cpuif_rd_ack(s_cpuif_rd_ack),
+    .m_cpuif_rd_err(s_cpuif_rd_err),
+    .m_cpuif_rd_data(s_cpuif_rd_data),
+    .m_cpuif_wr_ack(s_cpuif_wr_ack),
+    .m_cpuif_wr_err(s_cpuif_wr_err)
+);