Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_bitwise_reduce/regblock.rdl

@@ -0,0 +1,8 @@
+addrmap top {
+    reg {
+        field {
+            sw=rw; hw=r;
+            anded; ored; xored;
+        } f[7:0] = 0;
+    } r1;
+};

tests/test_bitwise_reduce/tb_template.sv

@@ -0,0 +1,44 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    cpuif.write('h0, 'h00);
+    @cb;
+    assert(cb.hwif_out.r1.f.anded == 1'b0);
+    assert(cb.hwif_out.r1.f.ored  == 1'b0);
+    assert(cb.hwif_out.r1.f.xored == 1'b0);
+
+    cpuif.write('h0, 'h01);
+    @cb;
+    assert(cb.hwif_out.r1.f.anded == 1'b0);
+    assert(cb.hwif_out.r1.f.ored  == 1'b1);
+    assert(cb.hwif_out.r1.f.xored == 1'b1);
+
+    cpuif.write('h0, 'h02);
+    @cb;
+    assert(cb.hwif_out.r1.f.anded == 1'b0);
+    assert(cb.hwif_out.r1.f.ored  == 1'b1);
+    assert(cb.hwif_out.r1.f.xored == 1'b1);
+
+    cpuif.write('h0, 'h03);
+    @cb;
+    assert(cb.hwif_out.r1.f.anded == 1'b0);
+    assert(cb.hwif_out.r1.f.ored  == 1'b1);
+    assert(cb.hwif_out.r1.f.xored == 1'b0);
+
+    cpuif.write('h0, 'hFE);
+    @cb;
+    assert(cb.hwif_out.r1.f.anded == 1'b0);
+    assert(cb.hwif_out.r1.f.ored  == 1'b1);
+    assert(cb.hwif_out.r1.f.xored == 1'b1);
+
+    cpuif.write('h0, 'hFF);
+    @cb;
+    assert(cb.hwif_out.r1.f.anded == 1'b1);
+    assert(cb.hwif_out.r1.f.ored  == 1'b1);
+    assert(cb.hwif_out.r1.f.xored == 1'b0);
+{% endblock %}

tests/test_bitwise_reduce/testcase.py

@@ -0,0 +1,5 @@
+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()