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Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

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Arnav Sacheti
2025-10-10 22:28:36 -07:00
commit 9bf5cd1e68
308 changed files with 19414 additions and 0 deletions
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0
tests/test_buffered_swacc_swmod/__init__.py Normal file
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60
tests/test_buffered_swacc_swmod/regblock.rdl Normal file
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addrmap top {
default regwidth = 16;
default accesswidth = 8;
reg {
buffer_reads;
field {
sw=r; hw=w;
swacc;
} f[16];
} r1;
reg {
buffer_reads;
buffer_writes;
field {
sw=rw; hw=r;
swmod;
} f[16] = 0x4020;
} r2;
reg {
buffer_reads;
buffer_writes;
field {
sw=rw; hw=r;
swmod;
rclr;
} f[16] = 0x1030;
} r3;
reg {
buffer_reads;
buffer_writes;
field {
sw=rw; hw=r;
swacc;
swmod;
} f[16] = 0x1234;
} r4;
reg {
buffer_writes;
field {
sw=rw; hw=r;
swacc;
swmod;
} f[16] = 0xABCD;
} r5;
reg {
buffer_reads;
field {
sw=r; hw=rw;
we;
swmod;
rclr;
} f[16] = 0x1030;
} r6;
};

197
tests/test_buffered_swacc_swmod/tb_template.sv Normal file
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{% extends "lib/tb_base.sv" %}
{% block seq %}
{% sv_line_anchor %}
logic [15:0] counter;
logic [7:0] rd_data_l;
logic [7:0] rd_data_h;
logic [15:0] latched_data;
int event_count;
bit fired;
latched_data = 'x;
##1;
cb.rst <= '0;
##1;
// Verify that hwif gets sampled at the same cycle as swacc strobe
counter = 'h10;
cb.hwif_in.r1.f.next <= counter;
@cb;
event_count = 0;
fork
begin
##0;
forever begin
counter++;
cb.hwif_in.r1.f.next <= counter;
@cb;
if(cb.hwif_out.r1.f.swacc) begin
latched_data = counter;
event_count++;
end
end
end
begin
cpuif.read('h0, rd_data_l);
cpuif.read('h1, rd_data_h);
repeat(3) @cb;
end
join_any
disable fork;
assert({rd_data_h, rd_data_l} == latched_data) else $error("Read returned 0x%0x but swacc strobed during 0x%0x", {rd_data_h, rd_data_l}, latched_data);
assert(event_count == 1) else $error("Observed excess swacc events: %0d", event_count);
// Verify that hwif changes 1 cycle after swmod
fired = 0;
fork
begin
##0;
forever begin
assert(cb.hwif_out.r2.f.value == 'h4020);
if(cb.hwif_out.r2.f.swmod) break;
@cb;
end
fired = 1;
@cb;
forever begin
assert(cb.hwif_out.r2.f.value == 'h4221);
assert(cb.hwif_out.r2.f.swmod == 0);
@cb;
end
end
begin
cpuif.write('h2, 'h21);
cpuif.write('h3, 'h42);
repeat(3) @cb;
end
join_any
disable fork;
assert(fired);
// Verify that hwif changes 1 cycle after swmod
fired = 0;
fork
begin
##0;
forever begin
assert(cb.hwif_out.r3.f.value == 'h1030);
if(cb.hwif_out.r3.f.swmod) break;
@cb;
end
fired = 1;
@cb;
forever begin
assert(cb.hwif_out.r3.f.value == 0);
assert(cb.hwif_out.r3.f.swmod == 0);
@cb;
end
end
begin
cpuif.assert_read('h4, 'h30);
cpuif.assert_read('h5, 'h10);
repeat(3) @cb;
end
join_any
disable fork;
assert(fired);
// Verify swacc and swmod assert when written
fired = 0;
fork
begin
##0;
forever begin
assert(cb.hwif_out.r4.f.value == 'h1234);
if(cb.hwif_out.r4.f.swmod || cb.hwif_out.r4.f.swacc) begin
assert(cb.hwif_out.r4.f.swmod == 1);
assert(cb.hwif_out.r4.f.swacc == 1);
break;
end
@cb;
end
fired = 1;
@cb;
forever begin
assert(cb.hwif_out.r4.f.value == 'h4567);
assert(cb.hwif_out.r4.f.swmod == 0);
assert(cb.hwif_out.r4.f.swacc == 0);
@cb;
end
end
begin
cpuif.write('h6, 'h67);
cpuif.write('h7, 'h45);
repeat(3) @cb;
end
join_any
disable fork;
assert(fired);
// Verify swacc and swmod assert when written
fired = 0;
fork
begin
##0;
forever begin
assert(cb.hwif_out.r5.f.value == 'hABCD);
if(cb.hwif_out.r5.f.swmod || cb.hwif_out.r5.f.swacc) begin
assert(cb.hwif_out.r5.f.swmod == 1);
assert(cb.hwif_out.r5.f.swacc == 1);
break;
end
@cb;
end
fired = 1;
@cb;
forever begin
assert(cb.hwif_out.r5.f.value == 'hEF12);
assert(cb.hwif_out.r5.f.swmod == 0);
assert(cb.hwif_out.r5.f.swacc == 0);
@cb;
end
end
begin
cpuif.write('h8, 'h12);
cpuif.write('h9, 'hEF);
repeat(3) @cb;
end
join_any
disable fork;
assert(fired);
// Verify that hwif changes 1 cycle after swmod
fired = 0;
fork
begin
##0;
forever begin
assert(cb.hwif_out.r6.f.value == 'h1030);
if(cb.hwif_out.r6.f.swmod) break;
@cb;
end
fired = 1;
@cb;
forever begin
assert(cb.hwif_out.r6.f.value == 0);
assert(cb.hwif_out.r6.f.swmod == 0);
@cb;
end
end
begin
cpuif.assert_read('ha, 'h30);
cpuif.assert_read('hb, 'h10);
repeat(3) @cb;
end
join_any
disable fork;
assert(fired);
{% endblock %}

5
tests/test_buffered_swacc_swmod/testcase.py Normal file
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from ..lib.sim_testcase import SimTestCase
class Test(SimTestCase):
def test_dut(self):
self.run_test()