Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_enum/regblock.rdl

@@ -0,0 +1,12 @@
+addrmap top {
+    enum my_enum {
+        val_1 = 3 {name = "Value 1";};
+        val_2 = 4 {desc = "Second value";};
+    };
+    reg {
+        field {
+            encode = my_enum;
+            sw=rw; hw=na;
+        } f[2:0] = my_enum::val_2;
+    } r0;
+};

tests/test_enum/tb_template.sv

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+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // check enum values
+    assert(regblock_pkg::top__my_enum__val_1 == 'd3);
+    assert(regblock_pkg::top__my_enum__val_2 == 'd4);
+
+    // check initial conditions
+    cpuif.assert_read('h0, regblock_pkg::top__my_enum__val_2);
+
+    //---------------------------------
+    // set r0 = val_1
+    cpuif.write('h0, regblock_pkg::top__my_enum__val_1);
+
+    cpuif.assert_read('h0, regblock_pkg::top__my_enum__val_1);
+
+{% endblock %}

tests/test_enum/testcase.py

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+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()