Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_hw_access/regblock.rdl

@@ -0,0 +1,73 @@
+addrmap top {
+    reg {
+        field {
+            sw=rw; hw=na;
+        } hw_enable[7:0] = 0xFF;
+
+        field {
+            sw=rw; hw=na;
+        } hw_mask[15:8] = 0x00;
+
+        field {
+            sw=rw; hw=na;
+        } hw_clr[16:16] = 0;
+
+        field {
+            sw=rw; hw=na;
+        } hw_set[17:17] = 0;
+
+        field {
+            sw=rw; hw=na;
+        } hw_we[18:18] = 0;
+
+        field {
+            sw=rw; hw=na;
+        } hw_wel[20:20] = 1;
+    } hw_ctrl;
+
+
+    reg {
+        field {
+            sw=r; hw=w;
+            we; hwclr; hwset;
+        } f[7:0] = 0x11;
+    } r1;
+    r1.f->hwenable = hw_ctrl.hw_enable;
+
+
+    reg {
+        field {
+            sw=r; hw=w;
+            we; hwclr; hwset;
+        } f[7:0] = 0x22;
+    } r2;
+    r2.f->hwmask = hw_ctrl.hw_mask;
+
+
+    reg {
+        field {
+            sw=rw; hw=w;
+        } f[7:0] = 0x33;
+    } r3;
+    r3.f->hwenable = hw_ctrl.hw_enable;
+    r3.f->hwclr = hw_ctrl.hw_clr;
+    r3.f->hwset = hw_ctrl.hw_set;
+    r3.f->we = hw_ctrl.hw_we;
+
+    reg {
+        field {
+            sw=rw; hw=w;
+        } f[7:0] = 0x44;
+    } r4;
+    r4.f->wel = hw_ctrl.hw_wel;
+
+    reg {
+        signal {} f_next_value[8];
+        signal {} f_we;
+        field {
+            sw=rw; hw=w;
+            next = f_next_value;
+            we = f_we;
+        } f[7:0] = 0x55;
+    } r5;
+};

tests/test_hw_access/tb_template.sv

@@ -0,0 +1,105 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // check initial conditions
+    cpuif.assert_read('h4, 'h11);
+    cpuif.assert_read('h8, 'h22);
+    cpuif.assert_read('hC, 'h33);
+
+    //---------------------------------
+    // set hwenable = F0
+    cpuif.write('h0, 'h00_F0);
+
+    // test hwenable + we
+    cb.hwif_in.r1.f.next <= 'hAB;
+    cb.hwif_in.r1.f.we <= '1;
+    @cb;
+    cb.hwif_in.r1.f.we <= '0;
+    cpuif.assert_read('h4, 'hA1);
+
+    // test hwenable + hwclr
+    cb.hwif_in.r1.f.hwclr <= '1;
+    @cb;
+    cb.hwif_in.r1.f.hwclr <= '0;
+    cpuif.assert_read('h4, 'h01);
+
+    // test hwenable + hwset
+    cb.hwif_in.r1.f.hwset <= '1;
+    @cb;
+    cb.hwif_in.r1.f.hwset <= '0;
+    cpuif.assert_read('h4, 'hF1);
+
+
+    //---------------------------------
+    // set hwmask = F0
+    cpuif.write('h0, 'hF0_00);
+
+    // test hwmask + we
+    cb.hwif_in.r2.f.next <= 'hAB;
+    cb.hwif_in.r2.f.we <= '1;
+    @cb;
+    cb.hwif_in.r2.f.we <= '0;
+    cpuif.assert_read('h8, 'h2B);
+
+    // test hwmask + hwclr
+    cb.hwif_in.r2.f.hwclr <= '1;
+    @cb;
+    cb.hwif_in.r2.f.hwclr <= '0;
+    cpuif.assert_read('h8, 'h20);
+
+    // test hwmask + hwset
+    cb.hwif_in.r2.f.hwset <= '1;
+    @cb;
+    cb.hwif_in.r2.f.hwset <= '0;
+    cpuif.assert_read('h8, 'h2F);
+
+    //---------------------------------
+    // test hwenable + hwclr via reference
+    // toggle hwenable = F0, hwclr=1
+    cpuif.write('h0, 'h1_00_F0);
+    cpuif.write('h0, 'h0_00_00);
+    cpuif.assert_read('hC, 'h03);
+
+    // test hwenable + hwset via reference
+    // toggle hwenable = 0F, hwset=1
+    cpuif.write('h0, 'h2_00_0F);
+    cpuif.write('h0, 'h0_00_00);
+    cpuif.assert_read('hC, 'h0F);
+
+    // test hwenable + we via reference
+    cb.hwif_in.r3.f.next <= 'hAA;
+    // toggle hwenable = 0F, we=1
+    cpuif.write('h0, 'h4_00_0F);
+    cpuif.write('h0, 'h0_00_00);
+    cpuif.assert_read('hC, 'h0A);
+
+    //---------------------------------
+    // test wel via reference
+    cb.hwif_in.r4.f.next <= 'hBB;
+    // toggle wel
+    cpuif.write('h0, 'h10_00_00);
+    cpuif.write('h0, 'h00_00_00);
+    cpuif.assert_read('h10, 'hBB);
+
+    cb.hwif_in.r4.f.next <= 'hCC;
+    // toggle wel
+    cpuif.write('h0, 'h10_00_00);
+    cpuif.write('h0, 'h00_00_00);
+    cpuif.assert_read('h10, 'hCC);
+
+    //---------------------------------
+    // test we and next via reference
+    cb.hwif_in.r5.f_next_value <= 'h54;
+    cpuif.assert_read('h14, 'h55);
+    cb.hwif_in.r5.f_next_value <= 'h56;
+    cb.hwif_in.r5.f_we <= '1;
+    @cb;
+    cb.hwif_in.r5.f_next_value <= '0;
+    cb.hwif_in.r5.f_we <= '0;
+    cpuif.assert_read('h14, 'h56);
+{% endblock %}

tests/test_hw_access/testcase.py

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+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()