Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_pipelined_cpuif/regblock.rdl

@@ -0,0 +1,8 @@
+addrmap regblock {
+    default sw=rw;
+    default hw=r;
+
+    reg {
+        field {} x[31:0] = 0;
+    } x[64] @ 0 += 4;
+};

tests/test_pipelined_cpuif/tb_template.sv

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+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // Write all regs in parallel burst
+    for(int i=0; i<64; i++) begin
+        fork
+            automatic int i_fk = i;
+            begin
+                cpuif.write(i_fk*4, i_fk + 32'h12340000);
+            end
+        join_none
+    end
+    wait fork;
+
+    // Verify HW value
+    @cb;
+    for(int i=0; i<64; i++) begin
+        assert(cb.hwif_out.x[i].x.value == i + 32'h12340000)
+            else $error("hwif_out.x[i] == 0x%0x. Expected 0x%0x", cb.hwif_out.x[i].x.value, i + 32'h12340000);
+    end
+
+    // Read all regs in parallel burst
+    for(int i=0; i<64; i++) begin
+        fork
+            automatic int i_fk = i;
+            begin
+                cpuif.assert_read(i_fk*4, i_fk + 32'h12340000);
+            end
+        join_none
+    end
+    wait fork;
+
+    // Mix read/writes
+    for(int i=0; i<8; i++) begin
+        fork
+            automatic int i_fk = i;
+            begin
+                cpuif.write(i_fk*4, i_fk + 32'h56780000);
+                cpuif.assert_read(i_fk*4, i_fk + 32'h56780000);
+            end
+        join_none
+    end
+    wait fork;
+
+{% endblock %}

tests/test_pipelined_cpuif/testcase.py

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+from parameterized import parameterized_class
+
+from ..lib.sim_testcase import SimTestCase
+from ..lib.test_params import get_permutations
+from ..lib.cpuifs import ALL_CPUIF
+
+@parameterized_class(get_permutations({
+    "cpuif": ALL_CPUIF,
+    "retime_read_fanin": [True, False],
+    "retime_read_response": [True, False],
+}))
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()