Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_pkg_params/regblock.rdl

@@ -0,0 +1,11 @@
+addrmap top #(
+    longint N_REGS = 1,
+    longint REGWIDTH = 32,
+    string NAME = "abcd"
+) {
+    reg reg_t {
+        regwidth = REGWIDTH;
+        field {sw=rw; hw=r;} f[REGWIDTH] = 1;
+    };
+    reg_t regs[N_REGS];
+};

tests/test_pkg_params/tb_template.sv

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+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    assert(regblock_pkg::N_REGS == {{testcase.n_regs}});
+    assert(regblock_pkg::REGWIDTH == {{testcase.regwidth}});
+    assert(regblock_pkg::NAME == "{{testcase.name}}");
+{% endblock %}

tests/test_pkg_params/testcase.py

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+from parameterized import parameterized_class
+
+from ..lib.sim_testcase import SimTestCase
+from ..lib.test_params import get_permutations
+
+PARAMS = get_permutations({
+    "n_regs" : [1, 2],
+    "regwidth" : [8, 16],
+    "name" : ["hello", "world"],
+})
+@parameterized_class(PARAMS)
+class TestRetimedFanin(SimTestCase):
+    n_regs = 20
+    regwidth = 32
+    name = "xyz"
+
+    @classmethod
+    def setUpClass(cls):
+        cls.rdl_elab_params = {
+            "N_REGS": cls.n_regs,
+            "REGWIDTH": cls.regwidth,
+            "NAME": f'"{cls.name}"',
+        }
+        super().setUpClass()
+
+    def test_dut(self):
+        self.run_test()