Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_precedence/regblock.rdl

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+addrmap top {
+    reg {
+        field {
+            sw=rw;
+            hw=w; we;
+            precedence=sw;
+        } f_sw = 0;
+        field {
+            sw=rw;
+            hw=w; we;
+            precedence=hw;
+        } f_hw = 0;
+    } r1 @ 0x0;
+
+    reg {
+        default counter;
+        default sw=r;
+        default hw=na;
+
+        field {} f_sw_count[3:0] = 0;
+        field {} f_hw_count[7:4] = 0;
+    } r1_events @ 0x4;
+
+    r1_events.f_sw_count->incr = r1.f_sw;
+    r1_events.f_hw_count->incr = r1.f_hw;
+};

tests/test_precedence/tb_template.sv

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+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // Always write both fields from hardware
+    cb.hwif_in.r1.f_sw.next <= '0;
+    cb.hwif_in.r1.f_sw.we <= '1;
+    cb.hwif_in.r1.f_hw.next <= '0;
+    cb.hwif_in.r1.f_hw.we <= '1;
+    @cb;
+    @cb;
+
+    cpuif.assert_read('h0, 'b00);
+    cpuif.assert_read('h4, 'h00);
+
+    cpuif.write('h0, 'b11);
+    cpuif.write('h0, 'b11);
+    cpuif.write('h0, 'b11);
+    cpuif.assert_read('h0, 'h00);
+    cpuif.assert_read('h4, 'h03);
+
+{% endblock %}

tests/test_precedence/testcase.py

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+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()