Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_read_fanin/regblock.rdl

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+addrmap top #(
+    longint N_REGS = 1,
+    longint REGWIDTH = 32
+) {
+    reg reg_t {
+        regwidth = REGWIDTH;
+        field {sw=rw; hw=na;} f[REGWIDTH] = 1;
+    };
+    reg_t regs[N_REGS];
+};

tests/test_read_fanin/tb_template.sv

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+{% extends "lib/tb_base.sv" %}
+
+{%- block declarations %}
+    {% sv_line_anchor %}
+    localparam REGWIDTH = {{testcase.regwidth}};
+    localparam STRIDE = REGWIDTH/8;
+    localparam N_REGS = {{testcase.n_regs}};
+{%- endblock %}
+
+
+{% block seq %}
+    {% sv_line_anchor %}
+    bit [REGWIDTH-1:0] data[N_REGS];
+
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    foreach(data[i]) data[i] = {$urandom(), $urandom(), $urandom(), $urandom()};
+
+    for(int i=0; i<N_REGS; i++) begin
+        cpuif.assert_read(i*STRIDE, 'h1);
+    end
+
+    for(int i=0; i<N_REGS; i++) begin
+        cpuif.write(i*STRIDE, data[i]);
+    end
+
+    for(int i=0; i<N_REGS; i++) begin
+        cpuif.assert_read(i*STRIDE, data[i]);
+    end
+
+    assert($bits(dut.cpuif_wr_data) == REGWIDTH);
+{% endblock %}

tests/test_read_fanin/testcase.py

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+from parameterized import parameterized_class
+
+from ..lib.sim_testcase import SimTestCase
+from ..lib.test_params import get_permutations
+
+
+PARAMS = get_permutations({
+    "regwidth" : [8, 16, 32, 64],
+})
+@parameterized_class(PARAMS)
+class TestFanin(SimTestCase):
+    retime_read_fanin = False
+    n_regs = 20
+    regwidth = 32
+
+    @classmethod
+    def setUpClass(cls):
+        cls.rdl_elab_params = {
+            "N_REGS": cls.n_regs,
+            "REGWIDTH": cls.regwidth,
+        }
+        super().setUpClass()
+
+    def test_dut(self):
+        self.run_test()
+
+
+PARAMS = get_permutations({
+    "n_regs" : [1, 4, 7, 9, 11],
+    "regwidth" : [8, 16, 32, 64],
+})
+@parameterized_class(PARAMS)
+class TestRetimedFanin(TestFanin):
+    retime_read_fanin = True
+
+    def test_dut(self):
+        self.run_test()