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Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

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This commit is contained in:
Arnav Sacheti
2025-10-10 22:28:36 -07:00
commit 9bf5cd1e68
308 changed files with 19414 additions and 0 deletions
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0
tests/test_reset_signals/__init__.py Normal file
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80
tests/test_reset_signals/regblock.rdl Normal file
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signal {
cpuif_reset; activehigh;
} root_cpuif_reset;
signal {} r5f2_resetvalue[16];
addrmap top {
reg {
field {
sw=rw; hw=na;
} f1[16] = 0x1234;
field {
sw=rw; hw=na;
} f2[16] = 0x5678;
} r1;
reg {
field {
sw=rw; hw=na;
} f1[16] = 0x1234;
field {
sw=rw; hw=na;
} f2[16] = 0x5678;
signal {
field_reset; activehigh; sync;
} my_reset;
} r2;
reg {
field {
sw=rw; hw=na;
} f1[16] = 0x1234;
field {
sw=rw; hw=na;
} f2[16] = 0x5678;
signal {
field_reset; activehigh; async;
} my_areset;
} r3;
reg {
field {
sw=rw; hw=na;
} f1[16] = 0x1234;
field {
sw=rw; hw=na;
} f2[16] = 0x5678;
signal {
field_reset; activelow; sync;
} my_reset_n;
} r4;
reg {
field {
sw=rw; hw=na;
} f1[16] = 0x1234;
field {
sw=rw; hw=na;
reset = r5f2_resetvalue;
} f2[16];
signal {
field_reset; activelow; async;
} my_areset_n;
} r5;
signal {
activehigh; sync;
} f2_reset;
r1.f2->resetsignal = f2_reset;
r2.f2->resetsignal = f2_reset;
r3.f2->resetsignal = f2_reset;
r4.f2->resetsignal = f2_reset;
r5.f2->resetsignal = f2_reset;
};

128
tests/test_reset_signals/tb_template.sv Normal file
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{% extends "lib/tb_base.sv" %}
{%- block declarations %}
logic root_cpuif_reset;
logic [15:0] r5f2_resetvalue;
{%- endblock %}
{%- block clocking_dirs %}
output root_cpuif_reset;
output r5f2_resetvalue;
{%- endblock %}
{% block seq %}
{% sv_line_anchor %}
cb.root_cpuif_reset <= '1;
cb.hwif_in.r2.my_reset <= '1;
cb.hwif_in.r3.my_areset <= '1;
cb.hwif_in.r4.my_reset_n <= '0;
cb.hwif_in.r5.my_areset_n <= '0;
cb.hwif_in.f2_reset <= '1;
cb.r5f2_resetvalue <= 'hABCD;
##2;
cb.rst <= '0;
cb.root_cpuif_reset <= '0;
cb.hwif_in.r2.my_reset <= '0;
cb.hwif_in.r3.my_areset <= '0;
cb.hwif_in.r4.my_reset_n <= '1;
cb.hwif_in.r5.my_areset_n <= '1;
cb.hwif_in.f2_reset <= '0;
##1;
cpuif.assert_read('h00, 'h5678_1234);
cpuif.assert_read('h04, 'h5678_1234);
cpuif.assert_read('h08, 'h5678_1234);
cpuif.assert_read('h0c, 'h5678_1234);
cpuif.assert_read('h10, 'hABCD_1234);
for(int i=0; i<5; i++) cpuif.write(i*4, 0);
cpuif.assert_read('h00, 'h0000_0000);
cpuif.assert_read('h04, 'h0000_0000);
cpuif.assert_read('h08, 'h0000_0000);
cpuif.assert_read('h0c, 'h0000_0000);
cpuif.assert_read('h10, 'h0000_0000);
cb.rst <= '1;
@cb;
cb.rst <= '0;
@cb;
cpuif.assert_read('h00, 'h0000_1234);
cpuif.assert_read('h04, 'h0000_0000);
cpuif.assert_read('h08, 'h0000_0000);
cpuif.assert_read('h0c, 'h0000_0000);
cpuif.assert_read('h10, 'h0000_0000);
for(int i=0; i<5; i++) cpuif.write(i*4, 0);
cb.hwif_in.r2.my_reset <= '1;
@cb;
cb.hwif_in.r2.my_reset <= '0;
@cb;
cpuif.assert_read('h00, 'h0000_0000);
cpuif.assert_read('h04, 'h0000_1234);
cpuif.assert_read('h08, 'h0000_0000);
cpuif.assert_read('h0c, 'h0000_0000);
cpuif.assert_read('h10, 'h0000_0000);
for(int i=0; i<5; i++) cpuif.write(i*4, 0);
##1;
#2ns;
hwif_in.r3.my_areset = '1;
#1ns;
hwif_in.r3.my_areset = '0;
##1;
cpuif.assert_read('h00, 'h0000_0000);
cpuif.assert_read('h04, 'h0000_0000);
cpuif.assert_read('h08, 'h0000_1234);
cpuif.assert_read('h0c, 'h0000_0000);
cpuif.assert_read('h10, 'h0000_0000);
for(int i=0; i<5; i++) cpuif.write(i*4, 0);
cb.hwif_in.r4.my_reset_n <= '0;
@cb;
cb.hwif_in.r4.my_reset_n <= '1;
@cb;
cpuif.assert_read('h00, 'h0000_0000);
cpuif.assert_read('h04, 'h0000_0000);
cpuif.assert_read('h08, 'h0000_0000);
cpuif.assert_read('h0c, 'h0000_1234);
cpuif.assert_read('h10, 'h0000_0000);
for(int i=0; i<5; i++) cpuif.write(i*4, 0);
##1;
#2ns;
hwif_in.r5.my_areset_n = '0;
#1ns;
hwif_in.r5.my_areset_n = '1;
##1;
cpuif.assert_read('h00, 'h0000_0000);
cpuif.assert_read('h04, 'h0000_0000);
cpuif.assert_read('h08, 'h0000_0000);
cpuif.assert_read('h0c, 'h0000_0000);
cpuif.assert_read('h10, 'h0000_1234);
for(int i=0; i<5; i++) cpuif.write(i*4, 0);
@cb;
cb.hwif_in.f2_reset <= '1;
cb.r5f2_resetvalue <= 'h3210;
@cb;
cb.hwif_in.f2_reset <= '0;
cpuif.assert_read('h00, 'h5678_0000);
cpuif.assert_read('h04, 'h5678_0000);
cpuif.assert_read('h08, 'h5678_0000);
cpuif.assert_read('h0c, 'h5678_0000);
cpuif.assert_read('h10, 'h3210_0000);
{% endblock %}

5
tests/test_reset_signals/testcase.py Normal file
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from ..lib.sim_testcase import SimTestCase
class Test(SimTestCase):
def test_dut(self):
self.run_test()