Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_singlepulse/regblock.rdl

@@ -0,0 +1,8 @@
+addrmap top {
+    reg {
+        field {
+            sw=rw; hw=r;
+            singlepulse;
+        } f[0:0] = 0;
+    } r1;
+};

tests/test_singlepulse/tb_template.sv

@@ -0,0 +1,56 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    int event_count;
+
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // No pulse if writing zero
+    event_count = 0;
+    fork
+        begin
+            ##0;
+            forever begin
+                @cb;
+                if(cb.hwif_out.r1.f.value) begin
+                    event_count++;
+                end
+            end
+        end
+
+        begin
+            cpuif.write('h0, 'h0);
+            repeat(5) @cb;
+        end
+    join_any
+    disable fork;
+    assert(event_count == 0) else $error("Observed excess singlepulse events: %0d", event_count);
+
+    // single pulse
+    event_count = 0;
+    fork
+        begin
+            ##0;
+            forever begin
+                @cb;
+                if(cb.hwif_out.r1.f.value) begin
+                    event_count++;
+                end
+            end
+        end
+
+        begin
+            cpuif.write('h0, 'h1);
+            repeat(5) @cb;
+        end
+    join_any
+    disable fork;
+    assert(event_count == 1) else $error("Observed incorrect number of singlepulse events: %0d", event_count);
+
+    // auto-clears
+    cpuif.assert_read('h0, 'h0);
+
+{% endblock %}

tests/test_singlepulse/testcase.py

@@ -0,0 +1,5 @@
+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()