Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_swwe/regblock.rdl

@@ -0,0 +1,66 @@
+addrmap top {
+    default regwidth = 8;
+
+    reg {
+        field {
+            sw=rw; hw=na;
+        } r3_swwe[0:0] = 1;
+
+        field {
+            sw=rw; hw=na;
+        } r4_swwel[1:1] = 0;
+    } lock;
+
+    //---------------------------------
+    // via inferred signal
+    //---------------------------------
+
+    reg {
+        field {
+            sw=rw; hw=na;
+            swwe;
+        } f[8] = 0x11;
+    } r1;
+
+    reg {
+        field {
+            sw=rw; hw=na;
+            swwel;
+        } f[8] = 0x22;
+    } r2;
+
+    //---------------------------------
+    // via lock register
+    //---------------------------------
+
+    reg {
+        field {
+            sw=rw; hw=na;
+        } f[8] = 0x33;
+    } r3;
+    r3.f->swwe = lock.r3_swwe;
+
+    reg {
+        field {
+            sw=rw; hw=na;
+        } f[8] = 0x44;
+    } r4;
+    r4.f->swwel = lock.r4_swwel;
+
+    //---------------------------------
+    // via prop ref chaining
+    //---------------------------------
+    reg {
+        field {
+            sw=rw; hw=na;
+        } f[8] = 0x55;
+    } r5;
+    r5.f->swwe = r3.f->swwe;
+
+    reg {
+        field {
+            sw=rw; hw=na;
+        } f[8] = 0x66;
+    } r6;
+    r6.f->swwe = r4.f->swwel; // intentionally opposite!
+};

tests/test_swwe/tb_template.sv

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+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // r1 swwe = true
+    cpuif.assert_read('h1, 'h11);
+    cb.hwif_in.r1.f.swwe <= '0;
+    cpuif.write      ('h1, 'h12);
+    cpuif.assert_read('h1, 'h11);
+    cb.hwif_in.r1.f.swwe <= '1;
+    cpuif.write      ('h1, 'h13);
+    cpuif.assert_read('h1, 'h13);
+
+    // r2 swwel = true
+    cpuif.assert_read('h2, 'h22);
+    cb.hwif_in.r2.f.swwel <= '1;
+    cpuif.write      ('h2, 'h23);
+    cpuif.assert_read('h2, 'h22);
+    cb.hwif_in.r2.f.swwel <= '0;
+    cpuif.write      ('h2, 'h24);
+    cpuif.assert_read('h2, 'h24);
+
+    // r3 swwe = lock.r3_swwe
+    cpuif.assert_read('h3, 'h33);
+    cpuif.write      ('h0, 'h0);
+    cpuif.write      ('h3, 'h32);
+    cpuif.assert_read('h3, 'h33);
+    cpuif.write      ('h0, 'h1);
+    cpuif.write      ('h3, 'h34);
+    cpuif.assert_read('h3, 'h34);
+
+    // r4 swwel = lock.r4_swwel
+    cpuif.assert_read('h4, 'h44);
+    cpuif.write      ('h0, 'h2);
+    cpuif.write      ('h4, 'h40);
+    cpuif.assert_read('h4, 'h44);
+    cpuif.write      ('h0, 'h0);
+    cpuif.write      ('h4, 'h45);
+    cpuif.assert_read('h4, 'h45);
+
+    // r5 swwe = r3->swwe = lock.r3_swwe
+    cpuif.assert_read('h5, 'h55);
+    cpuif.write      ('h0, 'h0);
+    cpuif.write      ('h5, 'h52);
+    cpuif.assert_read('h5, 'h55);
+    cpuif.write      ('h0, 'h1);
+    cpuif.write      ('h5, 'h54);
+    cpuif.assert_read('h5, 'h54);
+
+    // r6 swwe = r4->swwel = lock.r4_swwel
+    cpuif.assert_read('h6, 'h66);
+    cpuif.write      ('h0, 'h0);
+    cpuif.write      ('h6, 'h60);
+    cpuif.assert_read('h6, 'h66);
+    cpuif.write      ('h0, 'h2);
+    cpuif.write      ('h6, 'h65);
+    cpuif.assert_read('h6, 'h65);
+
+{% endblock %}

tests/test_swwe/testcase.py

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+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()