Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_validation_errors/external_ref.rdl

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+addrmap sub {
+    reg {
+        field {} f;
+    } x;
+};
+
+addrmap top {
+    reg {
+        field {} f;
+    } x;
+
+    sub sub;
+
+    x.f->reset = sub.x.f;
+};

tests/test_validation_errors/fixedpoint_counter.rdl

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+addrmap top {
+    reg {
+        field {
+            sw = rw; hw = r;
+            intwidth = 4;
+            counter;
+        } fixedpoint_counter[8] = 0;
+    } r1;
+};

tests/test_validation_errors/fixedpoint_enum.rdl

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+addrmap top {
+    reg {
+        enum test_enum {
+            zero = 2'b00;
+            one = 2'b01;
+            two = 2'b10;
+            three = 2'b11;
+        };
+        field {
+            sw = rw; hw = r;
+            fracwidth = 0;
+            encode = test_enum;
+        } fixedpoint_enum[2] = 0;
+    } r1;
+};

tests/test_validation_errors/fixedpoint_inconsistent_width.rdl

@@ -0,0 +1,9 @@
+addrmap top {
+    reg {
+        field {
+            sw = rw; hw = r;
+            intwidth = 4;
+            fracwidth = 5;
+        } num[8] = 0;
+    } r1;
+};

tests/test_validation_errors/inconsistent_accesswidth.rdl

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+addrmap top {
+    reg {
+        field {}f;
+    } x;
+    reg {
+        accesswidth = 16;
+        field {}f;
+    } y;
+};

tests/test_validation_errors/multiple_unconditional_assigns.rdl

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+addrmap top {
+    reg {
+        field {
+            sw = rw;
+            hw = w;
+            singlepulse = true;
+        } a = 0;
+        field {
+            sw = rw;
+            hw = w;
+            singlepulse = true;
+            posedge intr;
+            stickybit = false;
+        } b = 0;
+        field {
+            sw = rw;
+            hw = w;
+            singlepulse = true;
+            negedge intr;
+            stickybit = false;
+        } c = 0;
+        field {
+            sw = rw;
+            hw = w;
+            singlepulse = true;
+            bothedge intr;
+            stickybit = false;
+        } d = 0;
+    } x;
+};
+
+/*
+stickybit=false + intr posedge
+stickybit=false + intr negedge
+stickybit=false + intr bothedge
+hw=w wel = false
+singlepulse
+
+
+*/

tests/test_validation_errors/sharedextbus.rdl

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+addrmap top {
+    sharedextbus;
+
+    reg {
+        field {}f;
+    } x;
+};

tests/test_validation_errors/signed_counter.rdl

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+addrmap top {
+    reg {
+        field {
+            sw = rw; hw = r;
+            is_signed = false;
+            counter;
+        } unsigned_counter[8] = 0;
+        field {
+            sw = rw; hw = r;
+            is_signed;
+            counter;
+        } signed_counter[8] = 0;
+    } r1;
+};

tests/test_validation_errors/signed_enum.rdl

@@ -0,0 +1,20 @@
+addrmap top {
+    reg {
+        enum test_enum {
+            zero = 2'b00;
+            one = 2'b01;
+            two = 2'b10;
+            three = 2'b11;
+        };
+        field {
+            sw = rw; hw = r;
+            is_signed = false;
+            encode = test_enum;
+        } unsigned_enum[2] = 0;
+        field {
+            sw = rw; hw = r;
+            is_signed;
+            encode = test_enum;
+        } signed_enum[2] = 0;
+    } r1;
+};

tests/test_validation_errors/testcase.py

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+import io
+import contextlib
+
+from systemrdl.messages import RDLCompileError
+
+from ..lib.base_testcase import BaseTestCase
+
+class TestValidationErrors(BaseTestCase):
+    def setUp(self) -> None:
+        # Stub usual pre-test setup
+        pass
+
+    def tearDown(self):
+        # Delete any cruft that may get generated
+        self.delete_run_dir()
+
+    def assert_validate_error(self, rdl_file: str, err_regex: str) -> None:
+        self.rdl_file = rdl_file
+        f = io.StringIO()
+        with contextlib.redirect_stderr(f):
+            with self.assertRaises(RDLCompileError):
+                self.export_regblock()
+        stderr = f.getvalue()
+        self.assertRegex(stderr, err_regex)
+
+
+    def test_unaligned_reg(self) -> None:
+        self.assert_validate_error(
+            "unaligned_reg.rdl",
+            "Unaligned registers are not supported. Address offset of instance 'x' must be a multiple of 4",
+        )
+
+    def test_unaligned_stride(self) -> None:
+        self.assert_validate_error(
+            "unaligned_stride.rdl",
+            "Unaligned registers are not supported. Address stride of instance array 'x' must be a multiple of 4",
+        )
+
+    def test_bad_external_ref(self) -> None:
+        self.assert_validate_error(
+            "external_ref.rdl",
+            "Property is assigned a reference that points to a component not internal to the regblock being exported",
+        )
+
+    def test_sharedextbus_not_supported(self) -> None:
+        self.assert_validate_error(
+            "sharedextbus.rdl",
+            "This exporter does not support enabling the 'sharedextbus' property yet",
+        )
+
+    def test_inconsistent_accesswidth(self) -> None:
+        self.assert_validate_error(
+            "inconsistent_accesswidth.rdl",
+            r"Multi-word registers that have an accesswidth \(16\) that are inconsistent with this regblock's CPU bus width \(32\) are not supported",
+        )
+
+    def test_unbuffered_wide_w_fields(self) -> None:
+        self.assert_validate_error(
+            "unbuffered_wide_fields.rdl",
+            "Software-writable field 'xf' shall not span"
+            " multiple software-accessible subwords. Consider enabling"
+            " write double-buffering",
+        )
+
+    def test_unbuffered_wide_r_fields(self) -> None:
+        self.assert_validate_error(
+            "unbuffered_wide_fields.rdl",
+            "The field 'yf' spans multiple software-accessible"
+            " subwords and is modified on-read, making it impossible to"
+            " access its value correctly. Consider enabling read"
+            " double-buffering.",
+        )
+
+    def test_multiple_unconditional_assigns(self) -> None:
+        self.assert_validate_error(
+            "multiple_unconditional_assigns.rdl",
+            "Field has multiple conflicting properties that unconditionally set its state",
+        )
+
+    def test_unsynth_reset1(self) -> None:
+        self.assert_validate_error(
+            "unsynth_reset1.rdl",
+            "A field that uses an asynchronous reset cannot use a dynamic reset value. This is not synthesizable.",
+        )
+
+    def test_unsynth_reset2(self) -> None:
+        self.default_reset_async = True
+        self.assert_validate_error(
+            "unsynth_reset2.rdl",
+            "A field that uses an asynchronous reset cannot use a dynamic reset value. This is not synthesizable.",
+        )
+
+    def test_fixedpoint_counter(self) -> None:
+        self.assert_validate_error(
+            "fixedpoint_counter.rdl",
+            "Fixed-point representations are not supported for counter fields.",
+        )
+
+    def test_fixedpoint_enum(self) -> None:
+        self.assert_validate_error(
+            "fixedpoint_enum.rdl",
+            "Fixed-point representations are not supported for fields encoded as an enum.",
+        )
+
+    def test_fixedpoint_inconsistent_width(self) -> None:
+        self.assert_validate_error(
+            "fixedpoint_inconsistent_width.rdl",
+            r"Number of integer bits \(4\) plus number of fractional bits \(5\) must be equal to the width of the component \(8\).",
+        )
+
+    def test_signed_counter(self) -> None:
+        self.assert_validate_error(
+            "signed_counter.rdl",
+            "The property is_signed=true is not supported for counter fields.",
+        )
+
+    def test_signed_enum(self) -> None:
+        self.assert_validate_error(
+            "signed_enum.rdl",
+            "The property is_signed=true is not supported for fields encoded as an enum."
+        )

tests/test_validation_errors/unaligned_reg.rdl

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+addrmap top {
+    default regwidth = 32;
+    default accesswidth = 32;
+
+    reg {
+        field {}f;
+    } x @ 1;
+};

tests/test_validation_errors/unaligned_stride.rdl

@@ -0,0 +1,8 @@
+addrmap top {
+    default regwidth = 32;
+    default accesswidth = 32;
+
+    reg {
+        field {}f;
+    } x[4] @ 0 += 5;
+};

tests/test_validation_errors/unbuffered_wide_fields.rdl

@@ -0,0 +1,21 @@
+addrmap top {
+    reg {
+        regwidth = 64;
+        accesswidth = 32;
+        field {
+            sw=w;
+            hw=r;
+        } xf[64];
+    } x;
+
+    reg {
+        regwidth = 64;
+        accesswidth = 32;
+        field {
+            sw=r;
+            hw=w;
+            we;
+            onread=rclr;
+        } yf[64];
+    } y;
+};

tests/test_validation_errors/unsynth_reset1.rdl

@@ -0,0 +1,19 @@
+signal {
+    field_reset;
+    async;
+    activehigh;
+} foo;
+
+addrmap top {
+    reg {
+        field {
+            sw=rw; hw=na;
+        } f1;
+
+        field {
+            sw=rw; hw=na;
+        } f2;
+
+        f1->reset = f2;
+    } x;
+};

tests/test_validation_errors/unsynth_reset2.rdl

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+addrmap top {
+    reg {
+        field {
+            sw=rw; hw=na;
+        } f1;
+
+        field {
+            sw=rw; hw=na;
+        } f2;
+
+        f1->reset = f2;
+    } x;
+};