Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

2025-10-10 22:28:36 -07:00
commit 9bf5cd1e68
308 changed files with 19414 additions and 0 deletions
--- a/tests/test_write_buffer/init.py
+++ b/tests/test_write_buffer/init.py
--- a/tests/test_write_buffer/regblock.rdl
+++ b/tests/test_write_buffer/regblock.rdl
@@ -0,0 +1,106 @@
+addrmap top {
+    default regwidth = 16;
+    default accesswidth = 16;
+    default sw=rw;
+    default hw=r;
+    //--------------------------------------------------------------------------
+    // Wide registers
+    //--------------------------------------------------------------------------
+    reg {
+        regwidth = 64;
+        buffer_writes = true;
+        field {} f1[63:0] = 0;
+    } reg1;
+
+    reg {
+        regwidth = 64;
+        buffer_writes = true;
+        field {} f1[0:63] = 0;
+    } reg1_msb0;
+
+    reg {
+        regwidth = 32;
+        buffer_writes = true;
+        field {} f1[19:8] = 0;
+        field {} f2[23:20] = 0;
+    } reg2;
+
+    reg {
+        regwidth = 32;
+        buffer_writes = true;
+        field {} f1[8:19] = 0;
+        field {} f2[20:23] = 0;
+    } reg2_msb0;
+
+    //--------------------------------------------------------------------------
+    // Alternate Triggers
+    //--------------------------------------------------------------------------
+    reg myreg {
+        buffer_writes;
+        field {} f1[15:0] = 0;
+    };
+
+    // Trigger via another register
+    myreg g1_r1;
+    myreg g1_r2;
+    g1_r1->buffer_writes = false;
+    g1_r2->wbuffer_trigger = g1_r1;
+
+    // triger from signal
+    signal {
+        activehigh;
+    } trigger_sig;
+    signal {
+        activelow;
+    } trigger_sig_n;
+    myreg g2_r1;
+    myreg g2_r2;
+    g2_r1->wbuffer_trigger = trigger_sig;
+    g2_r2->wbuffer_trigger = trigger_sig_n;
+
+    // trigger from field
+    myreg g3_r1;
+    reg {
+        field {
+            sw=w; hw=r; singlepulse;
+        } trig = 0;
+    } g3_trig;
+    g3_r1->wbuffer_trigger = g3_trig.trig;
+
+    // trigger from propref
+    myreg g4_r1;
+    reg {
+        field {
+            hw=na;
+        } trig_vec[3:0] = 0;
+    } g4_trig;
+    g4_r1->wbuffer_trigger = g4_trig.trig_vec->anded;
+
+    //--------------------------------------------------------------------------
+    // swmod behavior
+    //--------------------------------------------------------------------------
+    myreg g5_r1;
+    g5_r1->wbuffer_trigger = trigger_sig;
+    reg {
+        field{
+            sw=rw;
+            hw=na;
+            counter;
+        } c[3:0] = 0;
+    } g5_modcount;
+    g5_modcount.c->incr = g5_r1.f1->swmod;
+
+    myreg g6_r1;
+    g6_r1.f1->rclr;
+    g6_r1->wbuffer_trigger = trigger_sig;
+    reg {
+        field{
+            sw=rw;
+            hw=na;
+            counter;
+        } c[3:0] = 0;
+    } g6_modcount;
+    g6_modcount.c->incr = g6_r1.f1->swmod;
+
+
+};
--- a/tests/test_write_buffer/tb_template.sv
+++ b/tests/test_write_buffer/tb_template.sv
@@ -0,0 +1,303 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    cb.hwif_in.trigger_sig_n <= '1;
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    //--------------------------------------------------------------------------
+    // Wide registers
+    //--------------------------------------------------------------------------
+
+    // reg1
+    cpuif.assert_read('h0, 'h0);
+    cpuif.assert_read('h2, 'h0);
+    cpuif.assert_read('h4, 'h0);
+    cpuif.assert_read('h6, 'h0);
+    assert(cb.hwif_out.reg1.f1.value == 0);
+    cpuif.write('h0, 'h1234);
+    cpuif.assert_read('h0, 'h0);
+    cpuif.assert_read('h2, 'h0);
+    cpuif.assert_read('h4, 'h0);
+    cpuif.assert_read('h6, 'h0);
+    assert(cb.hwif_out.reg1.f1.value == 0);
+    cpuif.write('h2, 'h5678);
+    cpuif.assert_read('h0, 'h0);
+    cpuif.assert_read('h2, 'h0);
+    cpuif.assert_read('h4, 'h0);
+    cpuif.assert_read('h6, 'h0);
+    assert(cb.hwif_out.reg1.f1.value == 0);
+    cpuif.write('h4, 'h9ABC);
+    cpuif.assert_read('h0, 'h0);
+    cpuif.assert_read('h2, 'h0);
+    cpuif.assert_read('h4, 'h0);
+    cpuif.assert_read('h6, 'h0);
+    assert(cb.hwif_out.reg1.f1.value == 0);
+    cpuif.write('h6, 'hDEF1);
+    @cb; @cb;
+    assert(cb.hwif_out.reg1.f1.value == 64'hDEF19ABC56781234);
+    cpuif.assert_read('h0, 'h1234);
+    cpuif.assert_read('h2, 'h5678);
+    cpuif.assert_read('h4, 'h9ABC);
+    cpuif.assert_read('h6, 'hDEF1);
+
+    // reg1_msb0
+    cpuif.assert_read('h8, 'h0);
+    cpuif.assert_read('hA, 'h0);
+    cpuif.assert_read('hC, 'h0);
+    cpuif.assert_read('hE, 'h0);
+    assert(cb.hwif_out.reg1_msb0.f1.value == 0);
+    cpuif.write('h8, 'h1234);
+    cpuif.assert_read('h8, 'h0);
+    cpuif.assert_read('hA, 'h0);
+    cpuif.assert_read('hC, 'h0);
+    cpuif.assert_read('hE, 'h0);
+    assert(cb.hwif_out.reg1_msb0.f1.value == 0);
+    cpuif.write('hA, 'h5678);
+    cpuif.assert_read('h8, 'h0);
+    cpuif.assert_read('hA, 'h0);
+    cpuif.assert_read('hC, 'h0);
+    cpuif.assert_read('hE, 'h0);
+    assert(cb.hwif_out.reg1_msb0.f1.value == 0);
+    cpuif.write('hC, 'h9ABC);
+    cpuif.assert_read('h8, 'h0);
+    cpuif.assert_read('hA, 'h0);
+    cpuif.assert_read('hC, 'h0);
+    cpuif.assert_read('hE, 'h0);
+    assert(cb.hwif_out.reg1_msb0.f1.value == 0);
+    cpuif.write('hE, 'hDEF1);
+    @cb; @cb;
+    assert(`bitswap(cb.hwif_out.reg1_msb0.f1.value) == 64'hDEF19ABC56781234);
+    cpuif.assert_read('h8, 'h1234);
+    cpuif.assert_read('hA, 'h5678);
+    cpuif.assert_read('hC, 'h9ABC);
+    cpuif.assert_read('hE, 'hDEF1);
+
+    // reg2
+    cpuif.assert_read('h10, 'h0);
+    cpuif.assert_read('h12, 'h0);
+    assert(cb.hwif_out.reg2.f1.value == 0);
+    assert(cb.hwif_out.reg2.f2.value == 0);
+    cpuif.write('h10, 'h34AA);
+    cpuif.assert_read('h10, 'h0);
+    cpuif.assert_read('h12, 'h0);
+    assert(cb.hwif_out.reg2.f1.value == 0);
+    assert(cb.hwif_out.reg2.f2.value == 0);
+    cpuif.write('h12, 'hAA12);
+    @cb; @cb;
+    assert(cb.hwif_out.reg2.f1.value == 12'h234);
+    assert(cb.hwif_out.reg2.f2.value == 4'h1);
+    cpuif.assert_read('h10, 'h3400);
+    cpuif.assert_read('h12, 'h0012);
+
+    // reg2_msb0
+    cpuif.assert_read('h14, 'h0);
+    cpuif.assert_read('h16, 'h0);
+    assert(cb.hwif_out.reg2_msb0.f1.value == 0);
+    assert(cb.hwif_out.reg2_msb0.f2.value == 0);
+    cpuif.write('h14, 'h34AA);
+    cpuif.assert_read('h14, 'h0);
+    cpuif.assert_read('h16, 'h0);
+    assert(cb.hwif_out.reg2_msb0.f1.value == 0);
+    assert(cb.hwif_out.reg2_msb0.f2.value == 0);
+    cpuif.write('h16, 'hAA12);
+    @cb; @cb;
+    assert(`bitswap(cb.hwif_out.reg2_msb0.f1.value) == 12'h234);
+    assert(`bitswap(cb.hwif_out.reg2_msb0.f2.value) == 4'h1);
+    cpuif.assert_read('h14, 'h3400);
+    cpuif.assert_read('h16, 'h0012);
+
+    //--------------------------------------------------------------------------
+    // Alternate Triggers
+    //--------------------------------------------------------------------------
+
+    // g1
+    cpuif.assert_read('h18, 'h0);
+    cpuif.assert_read('h1A, 'h0);
+    assert(cb.hwif_out.g1_r1.f1.value == 0);
+    assert(cb.hwif_out.g1_r2.f1.value == 0);
+    cpuif.write('h1A, 'h1234);
+    cpuif.assert_read('h18, 'h0);
+    cpuif.assert_read('h1A, 'h0);
+    assert(cb.hwif_out.g1_r1.f1.value == 0);
+    assert(cb.hwif_out.g1_r2.f1.value == 0);
+    cpuif.write('h18, 'hABCD);
+    @cb;
+    assert(cb.hwif_out.g1_r1.f1.value == 'hABCD);
+    assert(cb.hwif_out.g1_r2.f1.value == 'h1234);
+
+    // g2
+    cpuif.assert_read('h1C, 'h0);
+    cpuif.assert_read('h1E, 'h0);
+    assert(cb.hwif_out.g2_r1.f1.value == 0);
+    assert(cb.hwif_out.g2_r2.f1.value == 0);
+    cpuif.write('h1C, 'h5678);
+    cpuif.write('h1E, 'h9876);
+    cpuif.assert_read('h1C, 'h0);
+    cpuif.assert_read('h1E, 'h0);
+    assert(cb.hwif_out.g2_r1.f1.value == 0);
+    assert(cb.hwif_out.g2_r2.f1.value == 0);
+    cb.hwif_in.trigger_sig <= '1;
+    cb.hwif_in.trigger_sig_n <= '0;
+    @cb;
+    cb.hwif_in.trigger_sig <= '0;
+    cb.hwif_in.trigger_sig_n <= '1;
+    @cb;
+    assert(cb.hwif_out.g2_r1.f1.value == 'h5678);
+    assert(cb.hwif_out.g2_r2.f1.value == 'h9876);
+
+    // g3
+    cpuif.assert_read('h20, 'h0);
+    assert(cb.hwif_out.g3_r1.f1.value == 0);
+    cpuif.write('h20, 'hFEDC);
+    @cb; @cb;
+    assert(cb.hwif_out.g3_r1.f1.value == 0);
+    cpuif.assert_read('h20, 'h0);
+    cpuif.write('h22, 'h0000);
+    @cb; @cb;
+    assert(cb.hwif_out.g3_r1.f1.value == 0);
+    cpuif.assert_read('h20, 'h0);
+    cpuif.write('h22, 'h0001);
+    @cb; @cb;
+    assert(cb.hwif_out.g3_r1.f1.value == 'hFEDC);
+    cpuif.assert_read('h20, 'hFEDC);
+
+    // g4
+    cpuif.assert_read('h24, 'h0);
+    assert(cb.hwif_out.g4_r1.f1.value == 0);
+    cpuif.write('h24, 'hCAFE);
+    @cb; @cb;
+    assert(cb.hwif_out.g4_r1.f1.value == 0);
+    cpuif.assert_read('h24, 'h0);
+    cpuif.write('h26, 'h0000);
+    @cb; @cb;
+    assert(cb.hwif_out.g4_r1.f1.value == 0);
+    cpuif.assert_read('h24, 'h0);
+    cpuif.write('h26, 'h000E);
+    @cb; @cb;
+    assert(cb.hwif_out.g4_r1.f1.value == 0);
+    cpuif.assert_read('h24, 'h0);
+    cpuif.write('h26, 'h000F);
+    @cb; @cb;
+    assert(cb.hwif_out.g4_r1.f1.value == 'hCAFE);
+    cpuif.assert_read('h24, 'hCAFE);
+
+    //--------------------------------------------------------------------------
+    // swmod behavior
+    //--------------------------------------------------------------------------
+    // g5
+    cpuif.assert_read('h28, 'h0);
+    cpuif.assert_read('h2A, 'h0);
+    cpuif.write('h28, 'h1234);
+    cpuif.write('h28, 'h5678);
+    cpuif.assert_read('h28, 'h0);
+    cpuif.assert_read('h2A, 'h0);
+    cb.hwif_in.trigger_sig <= '1;
+    @cb;
+    cb.hwif_in.trigger_sig <= '0;
+    cpuif.assert_read('h28, 'h5678);
+    cpuif.assert_read('h2A, 'h1);
+
+    // g6
+    cpuif.assert_read('h2E, 'h0);
+    cpuif.assert_read('h2C, 'h0);
+    cpuif.assert_read('h2E, 'h1);
+    cpuif.write('h2C, 'h5678);
+    cpuif.write('h2C, 'h1234);
+    cpuif.assert_read('h2E, 'h1);
+    cpuif.assert_read('h2C, 'h0);
+    cpuif.assert_read('h2E, 'h2);
+    cb.hwif_in.trigger_sig <= '1;
+    @cb;
+    cb.hwif_in.trigger_sig <= '0;
+    cpuif.assert_read('h2E, 'h3);
+    cpuif.assert_read('h2C, 'h1234);
+    cpuif.assert_read('h2E, 'h4);
+
+    //--------------------------------------------------------------------------
+    // strobes
+    //--------------------------------------------------------------------------
+    // reg1
+    // reset field to known state
+    cpuif.write('h0, 'h0000);
+    cpuif.write('h2, 'h0000);
+    cpuif.write('h4, 'h0000);
+    cpuif.write('h6, 'h0000);
+    @cb;
+    cpuif.assert_read('h0, 'h0);
+    cpuif.assert_read('h2, 'h0);
+    cpuif.assert_read('h4, 'h0);
+    cpuif.assert_read('h6, 'h0);
+    assert(cb.hwif_out.reg1.f1.value == 0);
+
+    cpuif.write('h0, 'hABCD, 'hF000);
+    cpuif.write('h2, 'h1234, 'h0F00);
+    cpuif.write('h4, 'h5678, 'h00F0);
+    cpuif.write('h6, 'hEF12, 'h000F);
+    @cb;
+    cpuif.assert_read('h0, 'hA000);
+    cpuif.assert_read('h2, 'h0200);
+    cpuif.assert_read('h4, 'h0070);
+    cpuif.assert_read('h6, 'h0002);
+    assert(cb.hwif_out.reg1.f1.value == 'h0002_0070_0200_A000);
+
+    // Check that strobes are cumulative
+    cpuif.write('h0, 'h0030, 'h00F0);
+    cpuif.write('h2, 'h0070, 'h00F0);
+    cpuif.write('h4, 'h000D, 'h000F);
+    cpuif.write('h4, 'hA000, 'hF000);
+    cpuif.write('h2, 'h0008, 'h000F);
+    cpuif.write('h0, 'h0200, 'h0F00);
+    cpuif.write('h6, 'hA000, 'hF000);
+    cpuif.write('h6, 'h0F00, 'h0F00);
+    @cb;
+    cpuif.assert_read('h0, 'hA230);
+    cpuif.assert_read('h2, 'h0278);
+    cpuif.assert_read('h4, 'hA07D);
+    cpuif.assert_read('h6, 'hAF02);
+    assert(cb.hwif_out.reg1.f1.value == 'hAF02_A07D_0278_A230);
+
+    // reg1_msb0
+    // reset field to known state
+    cpuif.write('h8, 'h0000);
+    cpuif.write('hA, 'h0000);
+    cpuif.write('hC, 'h0000);
+    cpuif.write('hE, 'h0000);
+    @cb;
+    cpuif.assert_read('h8, 'h0);
+    cpuif.assert_read('hA, 'h0);
+    cpuif.assert_read('hC, 'h0);
+    cpuif.assert_read('hE, 'h0);
+    assert(cb.hwif_out.reg1_msb0.f1.value == 0);
+
+    cpuif.write('h8, 'hABCD, 'hF000);
+    cpuif.write('hA, 'h1234, 'h0F00);
+    cpuif.write('hC, 'h5678, 'h00F0);
+    cpuif.write('hE, 'hEF12, 'h000F);
+    @cb;
+    cpuif.assert_read('h8, 'hA000);
+    cpuif.assert_read('hA, 'h0200);
+    cpuif.assert_read('hC, 'h0070);
+    cpuif.assert_read('hE, 'h0002);
+    assert(`bitswap(cb.hwif_out.reg1_msb0.f1.value) == 'h0002_0070_0200_A000);
+
+    // Check that strobes are cumulative
+    cpuif.write('h8, 'h0030, 'h00F0);
+    cpuif.write('hA, 'h0070, 'h00F0);
+    cpuif.write('hC, 'h000D, 'h000F);
+    cpuif.write('hC, 'hA000, 'hF000);
+    cpuif.write('hA, 'h0008, 'h000F);
+    cpuif.write('h8, 'h0200, 'h0F00);
+    cpuif.write('hE, 'hA000, 'hF000);
+    cpuif.write('hE, 'h0F00, 'h0F00);
+    @cb;
+    cpuif.assert_read('h8, 'hA230);
+    cpuif.assert_read('hA, 'h0278);
+    cpuif.assert_read('hC, 'hA07D);
+    cpuif.assert_read('hE, 'hAF02);
+    assert(`bitswap(cb.hwif_out.reg1_msb0.f1.value) == 'hAF02_A07D_0278_A230);
+
+
+{% endblock %}
--- a/tests/test_write_buffer/testcase.py
+++ b/tests/test_write_buffer/testcase.py
@@ -0,0 +1,8 @@
+from ..lib.sim_testcase import SimTestCase
+from ..lib.cpuifs.passthrough import Passthrough
+
+class Test(SimTestCase):
+    cpuif = Passthrough() # test with bit strobes
+
+    def test_dut(self):
+        self.run_test()