This commit is contained in:
Arnav Sacheti
2025-10-19 21:52:12 -07:00
parent bafebf8595
commit eb5e64b151
4 changed files with 2 additions and 4 deletions

View File

@@ -65,7 +65,7 @@ class Exporter(ExporterSubcommandPlugin):
return cpuifs
def add_exporter_arguments(self, arg_group: "argparse.ArgumentParser") -> None: # type: ignore
def add_exporter_arguments(self, arg_group: "argparse.ArgumentParser") -> None: # type: ignore
cpuifs = self.get_cpuifs()
arg_group.add_argument(

View File

@@ -42,4 +42,4 @@ class APB3Cpuif(BaseCpuif):
if idx is not None:
return f"{base}[{idx}].{signal}"
raise ValueError("Must provide an index for arrayed interface signals")
raise ValueError("Must provide an index for arrayed interface signals")

View File

@@ -61,4 +61,3 @@ class APB3CpuifFlat(BaseCpuif):
if idx is not None:
return f"{base}_{signal}[{idx}]"
return f"{base}_{signal}[N_{node.inst_name.upper()}S]"

View File

@@ -148,7 +148,6 @@ class DesignValidator(RDLListener):
node.inst.inst_src_ref,
)
def exit_AddressableComponent(self, node: AddressableNode) -> None:
if not isinstance(node, RegNode):
# Exiting block-like node