bslathi19/PeakRDL-BusDecoder
1
0
Fork 0
Code Issues Actions Packages Projects Releases Wiki Activity

fanout/fainin wip

Browse Source
This commit is contained in:
Arnav Sacheti
2025-10-20 07:15:47 -07:00
parent e210167f2e
commit f956232a62
9 changed files with 147 additions and 132 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py
View File

@@ -1,5 +1,6 @@
from systemrdl.node import AddressableNode
from ...utils import get_indexed_path
from ..base_cpuif import BaseCpuif
@@ -26,20 +27,32 @@ class APB3Cpuif(BaseCpuif):
self,
signal: str,
node: AddressableNode | None = None,
idx: str | int | None = None,
) -> str:
if node is None:
# Node is none, so this is a slave signal
return f"s_apb.{signal}"
# Master signal
base = f"m_apb_{node.inst_name}"
if not node.is_array:
return f"{base}.{signal}"
if node.current_idx is not None:
# This is a specific instance of an array
return f"{base}_{'_'.join(map(str, node.current_idx))}.{signal}"
if idx is not None:
return f"{base}[{idx}].{signal}"
return f"m_apb_{node.inst_name}.{signal}"
raise ValueError("Must provide an index for arrayed interface signals")
def fanout(self, node: AddressableNode, idx: str | None = None) -> str:
fanout: dict[str, str] = {}
fanout[self.signal("PSEL", node, idx)] = (
f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node)}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node)}"
)
fanout[self.signal("PSEL", node, idx)] = self.signal("PSEL")
fanout[self.signal("PWRITE", node, idx)] = (
f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node)}"
)
fanout[self.signal("PADDR", node, idx)] = self.signal("PADDR")
fanout[self.signal("PWDATA", node, idx)] = "cpuif_wr_data"
return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
def fanin(self, node: AddressableNode, idx: str | None = None) -> str:
fanin: dict[str, str] = {}
fanin["cpuif_rd_data"] = self.signal("PRDATA", node, idx)
fanin["cpuif_rd_ack"] = self.signal("PREADY", node, idx)
fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, idx)
return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))

53
src/peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv
View File

@@ -11,47 +11,20 @@
assign cpuif_req = {{cpuif.signal("PSELx")}};
assign cpuif_wr_en = {{cpuif.signal("PWRITE")}};
assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
assign cpuif_rd_en = !{{cpuif.signal("PWRITE")}};
{%- for child in cpuif.addressable_children -%}
{%- if child is array -%}
for (genvar gi = 0; gi < N_{{child.inst_name|upper}}S; gi++) begin : g_passthrough_{{child.inst_name|lower}}
assign {{cpuif.signal("PCLK", child, "gi")}} = {{cpuif.signal("PCLK")}};
assign {{cpuif.signal("PRESETn", child, "gi")}} = {{cpuif.signal("PRESETn")}};
assign {{cpuif.signal("PSELx", child, "gi")}} = (cpuif_wr_req[{{loop.index}}] || cpuif_rd_req[{{loop.index}}]) ? 1'b1 : 1'b0;
assign {{cpuif.signal("PENABLE", child, "gi")}} = {{cpuif.signal("PENABLE")}};
assign {{cpuif.signal("PWRITE", child, "gi")}} = (cpuif_wr_req[{{loop.index}}]) ? 1'b1 : 1'b0;
assign {{cpuif.signal("PADDR", child, "gi")}} = {{child|address_slice(cpuif_addr="cpuif_wr_addr")}};
assign {{cpuif.signal("PWDATA", child, "gi")}} = cpuif_wr_data;
assign cpuif_rd_ack[loop.index] = {{cpuif.signal("PREADY", child)}};
assign cpuif_rd_data[loop.index] = {{cpuif.signal("PRDATA", child)}};
assign cpuif_rd_err[loop.index] = {{cpuif.signal("PSLVERR", child)}};
end
{%- else -%}
assign {{cpuif.signal("PCLK", child)}} = {{cpuif.signal("PCLK")}};
assign {{cpuif.signal("PRESETn", child)}} = {{cpuif.signal("PRESETn")}};
assign {{cpuif.signal("PSELx", child)}} = (cpuif_wr_sel[{{loop.index0}}] || cpuif_rd_sel[{{loop.index0}}]) ? 1'b1 : 1'b0;
assign {{cpuif.signal("PENABLE", child)}} = {{cpuif.signal("PENABLE")}};
assign {{cpuif.signal("PWRITE", child)}} = (cpuif_wr_req[{{loop.index}}]) ? 1'b1 : 1'b0;
assign {{cpuif.signal("PADDR", child)}} = {{child|address_slice(cpuif_addr="cpuif_wr_addr")}};
assign {{cpuif.signal("PWDATA", child)}} = cpuif_wr_data;
assign cpuif_rd_ack[loop.index] = {{cpuif.signal("PREADY", child)}};
assign cpuif_rd_data[loop.index] = {{cpuif.signal("PRDATA", child)}};
assign cpuif_rd_err[loop.index] = {{cpuif.signal("PSLVERR", child)}};
{%- endif -%}
{%- endfor%}
assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
always_comb begin
{{cpuif.signal("PREADY")}} = 1'b0;
{{cpuif.signal("PRDATA")}} = '0;
{{cpuif.signal("PSLVERR")}} = 1'b0;
assign {{cpuif.signal("PRDATA")}} = cpuif_rd_data;
assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack;
assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err;
for(int i = 0; i < {{cpuif.addressable_children | length}}; i++) begin
if (cpuif_rd_sel[i]) begin
{{cpuif.signal("PREADY")}} = cpuif_rd_ack[i];
{{cpuif.signal("PRDATA")}} = cpuif_rd_data[i];
{{cpuif.signal("PSLVERR")}} = cpuif_rd_err[i];
end
end
end
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
{{fanout|walk(cpuif=cpuif)}}
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
//--------------------------------------------------------------------------
{{fanin|walk(cpuif=cpuif)}}

36
src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py
View File

@@ -1,5 +1,6 @@
from systemrdl.node import AddressableNode
from ...utils import get_indexed_path
from ..base_cpuif import BaseCpuif
@@ -27,21 +28,34 @@ class APB4Cpuif(BaseCpuif):
self,
signal: str,
node: AddressableNode | None = None,
idx: str | int | None = None,
) -> str:
"""Returns the signal name for the given signal and node."""
if node is None:
# Node is none, so this is a slave signal
return f"s_apb.{signal}"
# Master signal
base = f"m_apb_{node.inst_name}"
if not node.is_array:
return f"{base}.{signal}"
if node.current_idx is not None:
# This is a specific instance of an array
return f"{base}_{'_'.join(map(str, node.current_idx))}.{signal}"
if idx is not None:
return f"{base}[{idx}].{signal}"
return f"m_apb_{node.inst_name}.{signal}"
raise ValueError("Must provide an index for arrayed interface signals")
def fanout(self, node: AddressableNode) -> str:
fanout: dict[str, str] = {}
fanout[f"m_apb_{get_indexed_path(node.parent, node, 'gi')}.PSEL"] = (
f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node)}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node)}"
)
fanout[f"m_apb_{get_indexed_path(node.parent, node, 'gi')}.PSEL"] = self.signal("PSEL")
fanout[f"m_apb_{get_indexed_path(node.parent, node, 'gi')}.PWRITE"] = (
f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
)
fanout[f"m_apb_{get_indexed_path(node.parent, node, 'gi')}.PADDR"] = self.signal("PADDR")
fanout[f"m_apb_{get_indexed_path(node.parent, node, 'gi')}.PPROT"] = self.signal("PPROT")
fanout[f"m_apb_{get_indexed_path(node.parent, node, 'gi')}.PWDATA"] = "cpuif_wr_data"
fanout[f"m_apb_{get_indexed_path(node.parent, node, 'gi')}.PSTRB"] = "cpuif_wr_byte_en"
return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
def fanin(self, node: AddressableNode) -> str:
fanin: dict[str, str] = {}
fanin["cpuif_rd_data"] = self.signal("PRDATA", node)
fanin["cpuif_rd_ack"] = self.signal("PREADY", node)
fanin["cpuif_rd_err"] = self.signal("PSLVERR", node)
return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))

69
src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
View File

@@ -11,72 +11,21 @@
assign cpuif_req = {{cpuif.signal("PSELx")}};
assign cpuif_wr_en = {{cpuif.signal("PWRITE")}};
assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
assign cpuif_rd_en = !{{cpuif.signal("PWRITE")}};
assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
assign cpuif_wr_byte_en = {{cpuif.signal("PSTRB")}};
assign {{cpuif.signal("PRDATA")}} = cpuif_rd_data;
assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack;
assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
// {%- for child in cpuif.addressable_children -%}
// {%- if child is array %}
// for (genvar gi = 0; gi < N_{{child.inst_name|upper}}S; gi++) begin : g_passthrough_{{child.inst_name|lower}}
// assign {{cpuif.signal("PCLK", child, "gi")}} = {{cpuif.signal("PCLK")}};
// assign {{cpuif.signal("PRESETn", child, "gi")}} = {{cpuif.signal("PRESETn")}};
// assign {{cpuif.signal("PSELx", child, "gi")}} = (cpuif_wr_sel[{{loop.index}}] || cpuif_rd_sel[{{loop.index}}]) ? 1'b1 : 1'b0;
// assign {{cpuif.signal("PENABLE", child, "gi")}} = {{cpuif.signal("PENABLE")}};
// assign {{cpuif.signal("PWRITE", child, "gi")}} = (cpuif_wr_sel[{{loop.index}}]) ? 1'b1 : 1'b0;
// assign {{cpuif.signal("PADDR", child, "gi")}} = {{child|address_slice(cpuif_addr="cpuif_wr_addr")}};
// assign {{cpuif.signal("PPROT", child, "gi")}} = {{cpuif.signal("PPROT")}};
// assign {{cpuif.signal("PWDATA", child, "gi")}} = cpuif_wr_data;
// assign {{cpuif.signal("PSTRB", child, "gi")}} = {{cpuif.signal("PSTRB")}};
// assign cpuif_rd_ack[{{loop.index}}] = {{cpuif.signal("PREADY", child, "gi")}};
// assign cpuif_rd_data[{{loop.index}}] = {{cpuif.signal("PRDATA", child, "gi")}};
// assign cpuif_rd_err[{{loop.index}}] = {{cpuif.signal("PSLVERR", child, "gi")}};
// end
// {%- else %}
// assign {{cpuif.signal("PCLK", child)}} = {{cpuif.signal("PCLK")}};
// assign {{cpuif.signal("PRESETn", child)}} = {{cpuif.signal("PRESETn")}};
// assign {{cpuif.signal("PSELx", child)}} = (cpuif_wr_sel[{{loop.index}}] || cpuif_rd_sel[{{loop.index}}]) ? 1'b1 : 1'b0;
// assign {{cpuif.signal("PENABLE", child)}} = {{cpuif.signal("PENABLE")}};
// assign {{cpuif.signal("PWRITE", child)}} = cpuif_wr_sel[{{loop.index}}] ? 1'b1 : 1'b0;
// assign {{cpuif.signal("PADDR", child)}} = {{child|address_slice(cpuif_addr="cpuif_wr_addr")}};
// assign {{cpuif.signal("PPROT", child)}} = {{cpuif.signal("PPROT")}};
// assign {{cpuif.signal("PWDATA", child)}} = cpuif_wr_data;
// assign {{cpuif.signal("PSTRB", child)}} = {{cpuif.signal("PSTRB")}};
// assign cpuif_rd_ack[{{loop.index}}] = {{cpuif.signal("PREADY", child)}};
// assign cpuif_rd_data[{{loop.index}}] = {{cpuif.signal("PRDATA", child)}};
// assign cpuif_rd_err[{{loop.index}}] = {{cpuif.signal("PSLVERR", child)}};
// {%- endif -%}
// {%- endfor %}
{{fanout|walk(cpuif=cpuif)}}
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
//--------------------------------------------------------------------------
always_comb begin
{{cpuif.signal("PREADY")}} = 1'b0;
{{cpuif.signal("PRDATA")}} = '0;
{{cpuif.signal("PSLVERR")}} = 1'b0;
{%- for child in cpuif.addressable_children -%}
{%- if loop.first %}
if (cpuif_rd_sel.{{child|get_path}}) begin
{%- else %}
end else if (cpuif_rd_sel.{{child|get_path}}) begin
{%- endif %}
{{cpuif.signal("PREADY")}} = cpuif_rd_ack[{{loop.index}}];
{{cpuif.signal("PRDATA")}} = cpuif_rd_data[{{loop.index}}];
{{cpuif.signal("PSLVERR")}} = cpuif_rd_err[{{loop.index}}];
{%- endfor %}
end
// for(int i = 0; i < {{cpuif.addressable_children | length}}; i++) begin
// if (cpuif_rd_sel[i]) begin
// {{cpuif.signal("PREADY")}} = cpuif_rd_ack[i];
// {{cpuif.signal("PRDATA")}} = cpuif_rd_data[i];
// {{cpuif.signal("PSLVERR")}} = cpuif_rd_err[i];
// end
// end
end
{{fanin|walk(cpuif=cpuif)}}

8
src/peakrdl_busdecoder/cpuif/base_cpuif.py
View File

@@ -106,8 +106,14 @@ class BaseCpuif:
return f"({cpuif_addr} - 'h{addr:x})[{clog2(size) - 1}:0]"
def walk(self, listener_cls: type[BusDecoderListener], **kwargs: Any) -> str:
def walk(self, listener_cls: type[BusDecoderListener], **kwargs: Any) -> str: # noqa: ANN401
walker = RDLSteerableWalker()
listener = listener_cls(self.exp.ds, **kwargs)
walker.walk(self.exp.ds.top_node, listener, skip_top=True)
return str(listener)
def fanout(self, node: AddressableNode) -> str:
raise NotImplementedError
def fanin(self, node: AddressableNode) -> str:
raise NotImplementedError

34
src/peakrdl_busdecoder/cpuif/fanin_gen.py
View File

@@ -1,19 +1,49 @@
from collections import deque
from typing import TYPE_CHECKING
from systemrdl.node import AddressableNode
from systemrdl.walker import WalkerAction
from ..body import Body, CombinationalBody, ForLoopBody
from ..design_state import DesignState
from ..listener import BusDecoderListener
from .base_cpuif import BaseCpuif
if TYPE_CHECKING:
from .base_cpuif import BaseCpuif
class FaninGenerator(BusDecoderListener):
def __init__(self, ds: DesignState, cpuif: BaseCpuif) -> None:
def __init__(self, ds: DesignState, cpuif: "BaseCpuif") -> None:
super().__init__(ds)
self._cpuif = cpuif
self._stack: deque[Body] = deque()
self._stack.append(CombinationalBody())
def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
action = super().enter_AddressableComponent(node)
if node.array_dimensions:
for i, dim in enumerate(node.array_dimensions):
fb = ForLoopBody(
"int",
f"i{i}",
dim,
)
self._stack.append(fb)
self._stack[-1] += self._cpuif.fanin(node)
return action
def exit_AddressableComponent(self, node: AddressableNode) -> None:
if node.array_dimensions:
for _ in node.array_dimensions:
b = self._stack.pop()
if not b:
continue
self._stack[-1] += b
super().exit_AddressableComponent(node)
def __str__(self) -> str:
return "\n".join(map(str, self._stack))

34
src/peakrdl_busdecoder/cpuif/fanout_gen.py
View File

@@ -1,19 +1,49 @@
from collections import deque
from typing import TYPE_CHECKING
from systemrdl.node import AddressableNode
from systemrdl.walker import WalkerAction
from ..body import Body, ForLoopBody
from ..design_state import DesignState
from ..listener import BusDecoderListener
from .base_cpuif import BaseCpuif
if TYPE_CHECKING:
from .base_cpuif import BaseCpuif
class FanoutGenerator(BusDecoderListener):
def __init__(self, ds: DesignState, cpuif: BaseCpuif) -> None:
def __init__(self, ds: DesignState, cpuif: "BaseCpuif") -> None:
super().__init__(ds)
self._cpuif = cpuif
self._stack: deque[Body] = deque()
self._stack.append(Body())
def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
action = super().enter_AddressableComponent(node)
if node.array_dimensions:
for i, dim in enumerate(node.array_dimensions):
fb = ForLoopBody(
"genvar",
f"gi{i}",
dim,
)
self._stack.append(fb)
self._stack[-1] += self._cpuif.fanout(node)
return action
def exit_AddressableComponent(self, node: AddressableNode) -> None:
if node.array_dimensions:
for _ in node.array_dimensions:
b = self._stack.pop()
if not b:
continue
self._stack[-1] += b
super().exit_AddressableComponent(node)
def __str__(self) -> str:
return "\n".join(map(str, self._stack))