04971bdb8e
* Initial plan * Fix non-synthesizable code for nested addrmaps with arrays Fixed bug where array dimensions were used instead of strides in decode logic. For nested addrmaps with arrays like inner[4] @ 0x0 += 0x100, the generated code was incorrectly using the dimension (4) instead of the stride (0x100). This resulted in non-synthesizable SystemVerilog with incorrect address decoding. The fix calculates proper strides for each dimension, including support for multi-dimensional arrays like [2][3] where each dimension has a different stride. Added comprehensive tests to prevent regression. Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Improve code comments for stride calculation clarity Added more detailed comments explaining the stride calculation logic, including a concrete example showing how strides are calculated for multi-dimensional arrays. Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
PeakRDL-BusDecoder
Generate a SystemVerilog bus decoder from SystemRDL that splits CPU interface signals to multiple sub-address spaces. This tool is designed for creating hierarchical register address maps by decoding bus transactions and routing them to the appropriate child address maps.
For the command line tool, see the PeakRDL project.
Documentation
See the PeakRDL-BusDecoder Documentation for more details