14 lines
1.3 KiB
Markdown
14 lines
1.3 KiB
Markdown
[](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/build.yml)
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[](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/test.yml)
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[](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/docs.yml)
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[](https://coveralls.io/github/arnavsacheti/PeakRDL-BusDecoder?branch=main)
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[](https://pypi.org/project/peakrdl-busdecoder)
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# PeakRDL-BusDecoder
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Generate a SystemVerilog bus decoder from SystemRDL that splits CPU interface signals to multiple sub-address spaces. This tool is designed for creating hierarchical register address maps by decoding bus transactions and routing them to the appropriate child address maps.
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For the command line tool, see the [PeakRDL project](https://peakrdl.readthedocs.io).
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## Documentation
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See the [PeakRDL-BusDecoder Documentation](https://peakrdl-busdecoder.readthedocs.io) for more details
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